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    Systems and methods for improving output signal quality in memory devices
    1.
    发明授权
    Systems and methods for improving output signal quality in memory devices 有权

    公开(公告)号：US10825506B2

    公开(公告)日：2020-11-03

    申请号：US15925399

    申请日：2018-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4076 ,  G11C7/10

    Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that may couple to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks to a controller. The semiconductor device may also include a plurality of switches that may couple a voltage source to the output buffer, a first pull-down switch that may drive the output buffer to a low voltage reference level to correct its drive strength. The device also includes a second pull-down switch that may couple the output buffer to the low voltage reference level. The plurality of switches, the first pull-down switch, and the second pull-down switch may each provide the data voltage signal to the output buffer.

    Memory device with a latching mechanism
    2.
    发明授权
    Memory device with a latching mechanism 有权

    公开(公告)号：US10395701B1

    公开(公告)日：2019-08-27

    申请号：US15975716

    申请日：2018-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho ,  Vijayakrishna J. Vankayala

    IPC: G11C7/22 ,  G11C11/4063 ,  G11C7/10

    Abstract: A memory device includes a timing circuit configured to: receive an input signal, wherein the input signal is one signal within a group of input signals (e.g., multiple bits or nibbles) that are communicated according to a sequence with each of the input signals individually in serial to parallel operations, and generate a grouped latching timing signal based on the received input signal, wherein the timing signal corresponds to nibbles of the data.

    SYSTEMS AND METHODS FOR IMPROVING OUTPUT SIGNAL QUALITY IN MEMORY DEVICES
    3.
    发明申请
    SYSTEMS AND METHODS FOR IMPROVING OUTPUT SIGNAL QUALITY IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20190259445A1

    公开(公告)日：2019-08-22

    申请号：US15925399

    申请日：2018-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho

    IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4096

    Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that may couple to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks to a controller. The semiconductor device may also include a plurality of switches that may couple a voltage source to the output buffer, a first pull-down switch that may drive the output buffer to a low voltage reference level to correct its drive strength. The device also includes a second pull-down switch that may couple the output buffer to the low voltage reference level. The plurality of switches, the first pull-down switch, and the second pull-down switch may each provide the data voltage signal to the output buffer.

    SYSTEMS AND METHODS FOR CONSERVING POWER IN SIGNAL QUALITY OPERATIONS FOR MEMORY DEVICES
    4.
    发明申请
    SYSTEMS AND METHODS FOR CONSERVING POWER IN SIGNAL QUALITY OPERATIONS FOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190259441A1

    公开(公告)日：2019-08-22

    申请号：US15924857

    申请日：2018-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho

    IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/50

    Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that couples to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks. The semiconductor device may also include a driver circuit having a pulse generator and a pull-down switch that couples the output buffer to ground, such that the pull-down switch provides the data voltage signal to the output buffer. The semiconductor device may also include a test mode circuit that determines whether the data voltage signal is acceptable and sends an enable signal to the pulse generator in response to the data voltage signal not being acceptable. The enable signal causes the pulse generator to effectively operate with variations in processing, temperature, and voltage properties associated with testing.

    Mitigating line-to-line capacitive coupling in a memory die
    5.
    发明授权
    Mitigating line-to-line capacitive coupling in a memory die 有权

    公开(公告)号：US10157661B1

    公开(公告)日：2018-12-18

    申请号：US15686996

    申请日：2017-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho ,  Scott E. Smith

    IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/22 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4091

    Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

    Memory with a reduced array data bus footprint
    7.
    发明授权
    Memory with a reduced array data bus footprint 有权

    公开(公告)号：US10790012B2

    公开(公告)日：2020-09-29

    申请号：US16432138

    申请日：2019-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho ,  Byung S. Moon

    IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/10

    Abstract: Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.

    Semiconductor device with pseudo flow through scheme for power savings
    8.
    发明授权
    Semiconductor device with pseudo flow through scheme for power savings 有权

    公开(公告)号：US10747470B2

    公开(公告)日：2020-08-18

    申请号：US15976724

    申请日：2018-05-10

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho ,  Ravi Kiran Kandikonda

    IPC: G06F12/00 ,  G06F3/06

    Abstract: A dynamic random-access memory (DRAM) device includes memory banks configured to store data and provide access to the stored data; and a data control circuit coupled to the memory banks, the data control circuit configured to: determine a pointer based on a received command, wherein the pointer corresponds to a target memory bank associated with the received command, and route a set of bits to or from the target memory bank using the pointer. In the long burst length and page mode operations where the array access is targeted in certain Bank Group, the pointer is generated and then allow the groups of data bits flowing through the center freely. This pseudo flow through scheme is low power and fast speed by removing the control of gating commands at each stage of the data path during Read and Write operations.

    MITIGATING LINE-TO-LINE CAPACITIVE COUPLING IN A MEMORY DIE
    9.
    发明申请
    MITIGATING LINE-TO-LINE CAPACITIVE COUPLING IN A MEMORY DIE 审中-公开

    公开(公告)号：US20190108869A1

    公开(公告)日：2019-04-11

    申请号：US16189434

    申请日：2018-11-13

    Applicant: Micron Technology, Inc.

    Inventor： Michael V. Ho ,  Scott E. Smith

    IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/22 ,  G11C11/408

    Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

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