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公开(公告)号：US20250013391A1
公开(公告)日：2025-01-09
申请号：US18773306
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Jameer Mulani , Jotiba Koparde
IPC: G06F3/06
Abstract: Methods, systems, and devices for managing single-level and multi-level programming operations are described. During a first duration, a first set of resources of a memory system may be configured for single-level operations and a second set of resources of a memory system may be configured to multi-level operations. Also, during the first duration, a first set of data may be received and written to a first virtual block that spans the first set of resources in accordance with a single-level programming operation. Additionally, during the first duration, a second set of data may be transferred from the first set of resources or the second set of resources to a second virtual block that spans the second set of resources in accordance with a multi-level programming operation.
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公开(公告)号：US20240053895A1
公开(公告)日：2024-02-15
申请号：US17887258
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Giuseppe Cariello , David Aaron Palmer
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0679 , G06F3/0629
Abstract: Methods, systems, and devices for improving write quality in memory systems are described. The memory system may receive, from a host system, a command to perform an operation. The memory system may determine an availability parameter that indicates processing resources of the memory system that are available to perform the operation based on receiving the command. In some cases, the memory system may transmit, to the host system, a message comprising the availability parameter, and the host system may delay transmission of one or more pending commands based on receiving the message comprising the availability parameter.
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公开(公告)号：US20250147695A1
公开(公告)日：2025-05-08
申请号：US18955746
申请日：2024-11-21
Applicant: Micron Technology, Inc.
Inventor： Reshmi Basu , Jonathan S. Parry , Nitul Gohain
Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
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公开(公告)号：US12169648B2
公开(公告)日：2024-12-17
申请号：US17888325
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Reshmi Basu , Jonathan S. Parry , Nitul Gohain
Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
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公开(公告)号：US20240289031A1
公开(公告)日：2024-08-29
申请号：US18581191
申请日：2024-02-19
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Nicola Colella
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679
Abstract: Methods, systems, and devices for data separation configurations for memory systems are described. A memory system may store one or more characteristics of data, which may be utilized to improve performance associated with transferring the data between blocks of memory cells. For example, a memory system may be configured to evaluate whether to separate data in one or more transfer operations based on the characteristics of the data. Some transfer configurations may include transferring data independent of characteristics of the data and some other transfer configurations may include transferring data based on characteristics of the data. In some examples, a transfer configuration may include transferring data associated with a relatively longer validity duration characteristic before transferring data associated with a relatively shorter validity duration characteristic, which may include transferring data associated with different validity duration characteristics to the same target block or to different target blocks.
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Patent Agency Ranking
公开(公告)号：US20240241790A1
公开(公告)日：2024-07-18
申请号：US18420888
申请日：2024-01-24
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Giuseppe Cariello , Jameer Mulani
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0632 , G06F3/0659 , G06F3/0679 , G06F11/0757 , G06F11/076 , G06F11/0772
Abstract: Methods, systems, and devices for determining locations in not-and (NAND) memory for boot-up code are described. An indication of one or more timeout durations for a boot sequence may be received. Information for the boot sequence may be stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells may be selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. The information for the boot sequence stored in the one or more memory cells may be accessed based on an initialization of the boot sequence.
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公开(公告)号：US20240220126A1
公开(公告)日：2024-07-04
申请号：US18395222
申请日：2023-12-22
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Nicola Colella , Jameer Mulani
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/064 , G06F3/0659 , G06F3/0679
Abstract: Methods, systems, and devices for folding operations for improved sequential read performance are described. A memory system may perform a single-die access operation to program data to source data blocks of the memory system. The memory system may reorder the data during folding to destination data blocks of the memory system such that a multi-die access operation may be performed to sequentially read the data from the destination data blocks. For example, data may be programmed to the source data blocks in a first order as part of a single-die access operation, and the data may be folded to the destination data blocks in a second order as part of a single-die access operation, where the supports sequentially reading the data from the destination data blocks as part of a multi-die access operation.
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公开(公告)号：US20240281144A1
公开(公告)日：2024-08-22
申请号：US18437076
申请日：2024-02-08
Applicant: Micron Technology, Inc.
Inventor： Nitul Gohain , Jameer Mulani , Amiya Banerjee
IPC: G06F3/06
CPC classification number: G06F3/0613 , G06F3/0659 , G06F3/0679
Abstract: Methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. A memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. The memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.
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公开(公告)号：US20240274215A1
公开(公告)日：2024-08-15
申请号：US18417737
申请日：2024-01-19
Applicant: Micron Technology, Inc.
Inventor： Giuseppe Cariello , Nitul Gohain , Jameer Mulani
IPC: G11C29/42
CPC classification number: G11C29/42
Abstract: Methods, systems, and devices for multi-level cell maintenance operations are described. A controller of a memory device may perform a two-portion maintenance operation in order to transfer data from a first block of memory cells to a second block of memory cells. For example, during a first portion of the maintenance operation, the controller may read first data from the first block of memory cells and perform a first error control operation to correct the first data. The controller may store second data associated with the first error control operation to volatile memory of the memory device in response to performing the first error control operation. During a second portion of the maintenance operation, the controller may perform a second error control operation using the second data associated with the first error control operations stored to the volatile memory of the memory device.
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公开(公告)号：US20240053925A1
公开(公告)日：2024-02-15
申请号：US17888325
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Reshmi Basu , Jonathan S. Parry , Nitul Gohain
CPC classification number: G06F3/0659 , G06F3/0634 , G06F3/0679 , G06F3/0604 , G06F12/0253
Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
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