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1.
公开(公告)号:US11768603B2
公开(公告)日:2023-09-26
申请号:US17662100
申请日:2022-05-05
Applicant: Micron Technology, Inc.
Inventor: Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
CPC classification number: G06F3/061 , G06F3/0644 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G11C7/1042 , G11C7/1045 , G11C8/12 , G11C16/08
Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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2.
公开(公告)号:US11354040B2
公开(公告)日:2022-06-07
申请号:US16926431
申请日:2020-07-10
Applicant: Micron Technology, Inc.
Inventor: Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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3.
公开(公告)号:US10719237B2
公开(公告)日:2020-07-21
申请号:US14992979
申请日:2016-01-11
Applicant: Micron Technology, Inc.
Inventor: Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
Abstract: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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