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公开(公告)号：US08860488B2
公开(公告)日：2014-10-14
申请号：US13787475
申请日：2013-03-06
发明人： Daniel Chu
IPC分类号： H03L5/00 , H03K19/003
CPC分类号： H03L5/00 , H03K3/35613 , H03K3/356139
摘要： Apparatuses and methods, such as those for shifting a voltage level are disclosed. An example apparatus includes a level shifter configured to provide output signals based on a logical value of an input signal, where the level shifter is precharged to a precharge voltage prior to providing the output signals. An example method includes precharging an output node of a level shifter to a precharge voltage responsive to a precharge signal via a precharge circuit. A transition of the input signal from a first logical value to a second logical value is received at the level shifter and an output signal is provided at the output node based on the second logical value of the input signal.
摘要翻译： 公开了用于移动电压电平的装置和方法。 示例性装置包括：电平移位器，被配置为基于输入信号的逻辑值提供输出信号，其中电平移位器在提供输出信号之前被预充电到预充电电压。 示例性方法包括：通过预充电电路将电平移位器的输出节点预充电到响应于预充电信号的预充电电压。 在电平移位器处接收从第一逻辑值到第二逻辑值的输入信号的转换，并且基于输入信号的第二逻辑值在输出节点处提供输出信号。
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公开(公告)号：US20140253209A1
公开(公告)日：2014-09-11
申请号：US13787475
申请日：2013-03-06
发明人： Daniel Chu
IPC分类号： H03K19/003 , H03L5/00
CPC分类号： H03L5/00 , H03K3/35613 , H03K3/356139
摘要： Apparatuses and methods, such as those for shifting a voltage level are disclosed. An example apparatus includes a level shifter configured to provide output signals based on a logical value of an input signal, where the level shifter is precharged to a precharge voltage prior to providing the output signals. An example method includes precharging an output node of a level shifter to a precharge voltage responsive to a precharge signal via a precharge circuit. A transition of the input signal from a first logical value to a second logical value is received at the level shifter and an output signal is provided at the output node based on the second logical value of the input signal.
摘要翻译： 公开了用于移动电压电平的装置和方法。 示例性装置包括：电平移位器，被配置为基于输入信号的逻辑值提供输出信号，其中电平移位器在提供输出信号之前被预充电到预充电电压。 示例性方法包括：通过预充电电路将电平移位器的输出节点预充电到响应于预充电信号的预充电电压。 在电平移位器处接收从第一逻辑值到第二逻辑值的输入信号的转换，并且基于输入信号的第二逻辑值在输出节点处提供输出信号。
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3.发明授权公开(公告)号：US11354040B2
公开(公告)日：2022-06-07
申请号：US16926431
申请日：2020-07-10
发明人： Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
摘要： Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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4.发明授权公开(公告)号：US10719237B2
公开(公告)日：2020-07-21
申请号：US14992979
申请日：2016-01-11
发明人： Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
摘要： Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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5.发明授权公开(公告)号：US11768603B2
公开(公告)日：2023-09-26
申请号：US17662100
申请日：2022-05-05
发明人： Rajesh Sundaram , Derchang Kau , Owen W. Jungroth , Daniel Chu , Raymond W. Zeng , Shekoufeh Qawami
CPC分类号： G06F3/061 , G06F3/0644 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G11C7/1042 , G11C7/1045 , G11C8/12 , G11C16/08
摘要： Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
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