公开(公告)号：US20190206727A1

公开(公告)日：2019-07-04

申请号：US16172218

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US20250159878A1

公开(公告)日：2025-05-15

申请号：US19022599

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20250159877A1

公开(公告)日：2025-05-15

申请号：US19022523

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H10B41/30 ,  H01L21/768 ,  H10B41/20 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20220189974A1

公开(公告)日：2022-06-16

申请号：US17654028

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US11088017B2

公开(公告)日：2021-08-10

申请号：US16806312

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3105 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US20190067306A1

公开(公告)日：2019-02-28

申请号：US15685690

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20250157935A1

公开(公告)日：2025-05-15

申请号：US19027625

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Chandra S. Tiwari

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H10B69/00

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

公开(公告)号：US12205900B2

公开(公告)日：2025-01-21

申请号：US17664385

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Chandra S. Tiwari

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H10B69/00

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

公开(公告)号：US20230378069A1

公开(公告)日：2023-11-23

申请号：US17664385

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Chandra S. Tiwari

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76837 ,  H01L27/115

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

公开(公告)号：US11282845B2

公开(公告)日：2022-03-22

申请号：US15685690

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.