公开(公告)号：US20210202299A1

公开(公告)日：2021-07-01

申请号：US16780594

申请日：2020-02-03

Applicant: Micron Technology, Inc.

Inventor： Jukuan Zheng ,  Sri Sai Sivakumar Vegunta ,  Kevin L. Baker ,  Josiah Jebaraj Johnley Muthuraj ,  Efe S. Ege

IPC: H01L21/768 ,  H01L27/24 ,  H01L27/108 ,  H01L45/00 ,  H01L21/67

Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.

公开(公告)号：US11770928B2

公开(公告)日：2023-09-26

申请号：US17662800

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  James A. Cultra ,  Sri Sai Sivakumar Vegunta

IPC: G11C11/00 ,  H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5384 ,  H10B43/27

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

公开(公告)号：US20190206727A1

公开(公告)日：2019-07-04

申请号：US16172218

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US11355508B2

公开(公告)日：2022-06-07

申请号：US16992959

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  James A. Cultra ,  Sri Sai Sivakumar Vegunta

IPC: G11C11/00 ,  H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  H01L27/11582

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

公开(公告)号：US20220068702A1

公开(公告)日：2022-03-03

申请号：US17524638

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Jukuan Zheng ,  Sri Sai Sivakumar Vegunta ,  Kevin L. Baker ,  Josiah Jebaraj Johnley Muthuraj ,  Efe S. Ege

IPC: H01L21/768 ,  H01L27/24 ,  H01L27/108 ,  H01L21/67 ,  H01L45/00 ,  G11C5/06

Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.

公开(公告)号：US10600682B2

公开(公告)日：2020-03-24

申请号：US16172218

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3105 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US10269625B1

公开(公告)日：2019-04-23

申请号：US15857197

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.

公开(公告)号：US11735473B2

公开(公告)日：2023-08-22

申请号：US17524638

申请日：2021-11-11

Applicant: Micron Technology, Inc.

Inventor： Jukuan Zheng ,  Sri Sai Sivakumar Vegunta ,  Kevin L. Baker ,  Josiah Jebaraj Johnley Muthuraj ,  Efe S. Ege

IPC: H01L21/768 ,  H01L21/67 ,  G11C5/06 ,  H10B12/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H01L21/7684 ,  G11C5/06 ,  H01L21/67075 ,  H10B12/09 ,  H10B63/00 ,  H10N70/801 ,  H10N70/882 ,  H10N70/883

Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.

公开(公告)号：US20220271052A1

公开(公告)日：2022-08-25

申请号：US17662800

申请日：2022-05-10

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  James A. Cultra ,  Sri Sai Sivakumar Vegunta

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/538 ,  H01L27/11582

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

公开(公告)号：US11201083B2

公开(公告)日：2021-12-14

申请号：US16780594

申请日：2020-02-03

Applicant: Micron Technology, Inc.

Inventor： Jukuan Zheng ,  Sri Sai Sivakumar Vegunta ,  Kevin L. Baker ,  Josiah Jebaraj Johnley Muthuraj ,  Efe S. Ege

IPC: H01L21/768 ,  H01L27/24 ,  H01L27/108 ,  H01L21/67 ,  H01L45/00 ,  G11C5/06

Abstract: Methods of manufacturing memory devices having memory cells and corresponding selectors, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a memory device includes (a) removing a protection layer formed over the memory cells and (b) forming a cap layer over the memory cells before forming a conductive via through the memory device. The cap layer is configured to protect the memory cells during operation and can comprise a resistive material. The protection layer can be more efficiently removed with improved process margin and less device health impact using a polishing process before the conductive via is formed, thus increasing the manufacturing margin of the memory device.