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公开(公告)号：US11990199B2
公开(公告)日：2024-05-21
申请号：US17647152
申请日：2022-01-05
Applicant: Micron Technology, Inc.
Inventor： Taeksang Song , Saira Samar Malik , Hyunyoo Lee , Chinnakrishnan Ballapuram , Kang-Yong Kim
CPC classification number: G11C29/42 , G11C29/1201 , G11C29/4401
Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.
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公开(公告)号：US11972145B2
公开(公告)日：2024-04-30
申请号：US17570024
申请日：2022-01-06
Applicant: Micron Technology, Inc.
Inventor： Saira Samar Malik , Chinnakrishnan Ballapuram , Taeksang Song
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and devices for opportunistic data movement are described. A memory device may include a non-volatile memory and a volatile memory that operates as a cache for the non-volatile memory. The memory device may receive a write command from a host device. The write command may be associated with a row of a bank in a volatile memory. The memory device may write data associated with the write command to a buffer that is associated with the bank and that is coupled with the volatile memory. And the memory device may communicate the data from the buffer to the volatile memory based on the write command and before a pre-charge command for the row of the bank is received from the host device.
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公开(公告)号：US11797231B2
公开(公告)日：2023-10-24
申请号：US17584104
申请日：2022-01-25
Applicant: Micron Technology, Inc.
Inventor： Taeksang Song , Saira Samar Malik , Chinnakrishnan Ballapuram
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/068 , G06F3/0614
Abstract: Methods, systems, and devices for hazard detection in a multi-memory device are described. A device may receive a first command that indicates a first bank address, a first row address, and a first column address. Based on the first bank address, the device may select a buffer for a hazard detection procedure that detects hazardous commands. The device may compare, as part of the hazard detection procedure, the first row address and the first column address from the first command with a second row address and a second column address from a second command in the buffer. The device may determine whether the first command and the second command are hazardous commands based on comparing the first row address and the first column address from the first command with the second row address and the second column address from the second command.
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公开(公告)号：US20220011944A1
公开(公告)日：2022-01-13
申请号：US17349634
申请日：2021-06-16
Applicant: Micron Technology, Inc.
Inventor： Saira Samar Malik , Hyunyoo Lee , Chinnakrishnan Ballapuram , Taeksang Song , Kang-Yong Kim
Abstract: Methods, systems, and devices for memory wear management are described. A device may include an interface controller and a non-volatile memory. The interface controller may manage wear-leveling procedures for memory banks in the non-volatile memory. For example, the interface controller may select a row in a memory bank for the wear-leveling procedure. The interface controller may store data from the row in a buffer in the interface controller. The interface controller may then transfer the data to the non-volatile memory so that the non-volatile memory can write the data to a second row of the memory bank.
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公开(公告)号：US11853609B2
公开(公告)日：2023-12-26
申请号：US17585298
申请日：2022-01-26
Applicant: Micron Technology, Inc.
Inventor： Taeksang Song , Saira Samar Malik , Chinnakrishnan Ballapuram
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0625 , G06F3/0656 , G06F3/0679
Abstract: Methods, systems, and devices for power mode control in a multi-memory device are described. An apparatus may include a non-volatile memory and a volatile memory. The apparatus may operate the volatile memory in a first power mode and the non-volatile memory in a second power mode. The apparatus may transition the volatile memory from the first power mode to a third power mode based on a power mode command from a host device. The apparatus may transition the non-volatile memory from the second power mode to a fourth power mode that consumes less power than the second power mode irrespective of the command from the host device and based on a quantity of queued commands for the non-volatile memory being less than a threshold quantity.
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Patent Agency Ranking
公开(公告)号：US11748033B2
公开(公告)日：2023-09-05
申请号：US17390093
申请日：2021-07-30
Applicant: Micron Technology, Inc.
Inventor： Chinnakrishnan Ballapuram , Kang-Yong Kim , Saira Samar Malik , Taeksang Song
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G06F12/0238
Abstract: Methods, systems, and devices for transaction management using metadata are described. In some examples, a memory device may include a volatile memory, and a non-volatile memory, which may have different access latencies. The memory device may receive from a host device a read command for data located at an address of the non-volatile memory. In response to the read command, the memory device and may determine whether the data is stored in the volatile memory. The memory device may then transmit, to the host device data and according to an expected latency, a set of data and an indication of whether the set of data was previously requested by the host device or unrequested by the host device. In some examples, the memory device may also transmit an identifier associated with the read command and a hash of the address.
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公开(公告)号：US20220300173A1
公开(公告)日：2022-09-22
申请号：US17648398
申请日：2022-01-19
Applicant: Micron Technology, Inc.
Inventor： Saira Samar Malik , Chinnakrishnan Ballapuram , Taeksang Song
IPC: G06F3/06
Abstract: Methods, systems, and devices for strategic power mode transition in a multi-memory device are described. A controller may receive, from a host device, a command indicating that the controller is to transition a volatile memory and a non-volatile memory from respective deep sleep modes. In a first example, the controller may respond to the command by transitioning the volatile memory to a standby power mode for the volatile memory and transitioning the non-volatile memory to an intermediate power mode for the non-volatile memory that consumes less power than a standby mode for the non-volatile memory. In a second example, the controller may respond to the command by transitioning the volatile memory to the standby power mode for the volatile memory and maintain the non-volatile memory in the deep sleep mode until a condition, such as a miss, occurs.
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公开(公告)号：US20220230698A1
公开(公告)日：2022-07-21
申请号：US17647152
申请日：2022-01-05
Applicant: Micron Technology, Inc.
Inventor： Taeksang Song , Saira Samar Malik , Hyunyoo Lee , Chinnakrishnan Ballapuram , Kang-Yong Kim
Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.
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公开(公告)号：US20220066961A1
公开(公告)日：2022-03-03
申请号：US17395303
申请日：2021-08-05
Applicant: Micron Technology, Inc.
Inventor： Saira Samar Malik , Taeksang Song , Chinnakrishnan Ballapuram
Abstract: Methods, systems, and devices for an efficient turnaround policy for a bus are described. A device may include a memory and a bus for communicating with the memory. The device may operate the bus in a first direction, relative to the memory, that is associated with a first type of access command. The device may determine, for the memory, that a quantity of queued access commands of a second type are for one or more banks that have satisfied a timing constraint for activating different rows in a same bank. Based on determining that the quantity of queued access commands of the second type are for one or more banks that have satisfied the timing constraint, the device may operate the bus in a second direction, relative to the memory, that is associated with the second type of access command.
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公开(公告)号：US20240347123A1
公开(公告)日：2024-10-17
申请号：US18647867
申请日：2024-06-07
Applicant: Micron Technology, Inc.
Inventor： Taeksang Song , Saira Samar Malik , Hyunyoo Lee , Chinnakrishnan Ballapuram , Kang-Yong Kim
CPC classification number: G11C29/42 , G11C29/1201 , G11C29/4401
Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.
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