公开(公告)号：US20250126773A1

公开(公告)日：2025-04-17

申请号：US18999244

申请日：2024-12-23

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: H10B12/00 ,  G11C11/4096 ,  G11C29/54 ,  H10D30/67

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US11985806B2

公开(公告)日：2024-05-14

申请号：US16721380

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Srinivas Pulugurtha ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/108 ,  H10B12/00 ,  G11C11/402

CPC classification number: H10B12/01 ,  G11C11/4023

Abstract: Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

公开(公告)号：US20220310620A1

公开(公告)日：2022-09-29

申请号：US17215904

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: H01L27/108 ,  G11C11/4096 ,  H01L29/786 ,  G11C29/54

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US20220069083A1

公开(公告)日：2022-03-03

申请号：US17453621

申请日：2021-11-04

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Jaydip Guha ,  Scott E. Sills ,  Yi Fang Lee

IPC: H01L29/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/11502 ,  H01L29/24 ,  H01L27/108

Abstract: Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The active region has a first region, a third region offset from the first region, and a second region between the first and third regions. A gating structure is operatively adjacent to the second region. A first carrier-concentration-gradient is within the first region, and a second carrier-concentration-gradient is within the third region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210375925A1

公开(公告)日：2021-12-02

申请号：US17445157

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra V. Mouli ,  Srinivas Pulugurtha

IPC: H01L27/11582 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/04 ,  H01L29/165 ,  H01L29/66 ,  H01L29/22 ,  H01L21/28

Abstract: Memory devices and electronic systems include an array of vertical memory cells positioned along respective vertical channels to define vertical memory strings. Each of the vertical channels includes a channel material exhibiting an electron mobility of at least about 30 cm2/(V·s) and a room temperature band gap of at least about 1.40 eV (e.g., zinc oxide, silicon carbide, indium phosphide, indium gallium zinc oxide, gallium arsenide, or molybdenum disulfide) and a bottom plug material exhibiting a room temperature band gap of less than about 1.10 eV (e.g., silicon germanium, germanium, or indium gallium arsenide). Methods of fabricating a memory device include forming such a bottom plug material within vertical channels and forming such a channel material electrically coupled to the bottom plug material.

公开(公告)号：US20210351087A1

公开(公告)日：2021-11-11

申请号：US16868133

申请日：2020-05-06

Applicant: Micron Technology, Inc.

Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Yunfei Gao ,  Sanh D. Tang ,  Haitao Liu

IPC: H01L21/84 ,  H01L21/265

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11164872B1

公开(公告)日：2021-11-02

申请号：US16943163

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Litao Yang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/108 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/265

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. An underbody conductive contact of a vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the horizontally oriented digit lines by a dielectric.

公开(公告)号：US20200286895A1

公开(公告)日：2020-09-10

申请号：US16809924

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200176564A1

公开(公告)日：2020-06-04

申请号：US16209495

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Yunfei Gao ,  Srinivas Pulugurtha

IPC: H01L29/08 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

Abstract: An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.

公开(公告)号：US20190206870A1

公开(公告)日：2019-07-04

申请号：US15898086

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Haitao Liu ,  Deepak Chandra Pandey ,  Srinivas Pulugurtha ,  Kamal M. Karda

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/423

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.