公开(公告)号：US20230397406A1

公开(公告)日：2023-12-07

申请号：US17848107

申请日：2022-06-23

Applicant: Micron Technology, Inc

Inventor： Sau Ha Cheung ,  Soichi Sugiura ,  Jaydip Guha ,  Anthony J. Kanago ,  Richard Beeler

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a recess formed in a semiconductor material; a dielectric structure formed in the recess; and a control gate for a transistor of a memory cell, the control gate including a first conductive portion formed in the recess and separated from the semiconductor material by a first portion of the dielectric structure, the first dielectric portion including a first dielectric material between the semiconductor material and the second dielectric material, and a second dielectric material between the first dielectric material and the first conductive portion; and the control gate including the second conductive portion formed over the first conductive portion and separated from the semiconductor material by a second portion of the dielectric structure between the semiconductor material and second conductive portion.

公开(公告)号：US12178033B2

公开(公告)日：2024-12-24

申请号：US17215904

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: G11C11/40 ,  G11C11/4096 ,  G11C29/54 ,  H01L29/786 ,  H10B12/00

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US20250126773A1

公开(公告)日：2025-04-17

申请号：US18999244

申请日：2024-12-23

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: H10B12/00 ,  G11C11/4096 ,  G11C29/54 ,  H10D30/67

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US20220310620A1

公开(公告)日：2022-09-29

申请号：US17215904

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Anthony J. Kanago ,  Jaydip Guha ,  Srinivas Pulugurtha ,  Soichi Sugiura

IPC: H01L27/108 ,  G11C11/4096 ,  H01L29/786 ,  G11C29/54

Abstract: Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.

公开(公告)号：US20240381628A1

公开(公告)日：2024-11-14

申请号：US18659367

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Anthony J. Kanago

IPC: H10B12/00

Abstract: A variety of applications can include a memory device having a memory array region on a memory die and a periphery to the memory array region on the memory die, where the periphery can include a fully depleted silicon-on-insulator (FDSOI) complementary metal-oxide-semiconductor (CMOS) device. A metal shield can be integrated in the memory array region, where the metal shield is structured as a shield to digit lines of the memory array. A metal body plate in the periphery can be structured as a back gate to the FDSOI CMOS device.

公开(公告)号：US20240274113A1

公开(公告)日：2024-08-15

申请号：US18417273

申请日：2024-01-19

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Anthony J. Kanago

IPC: G10K11/178 ,  H04R1/10

CPC classification number: G10K11/17823 ,  G10K11/17827 ,  G10K11/17873 ,  H04R1/1041 ,  H04R1/1083 ,  G10K2210/1081 ,  G10K2210/30231 ,  G10K2210/3027 ,  G10K2210/3028 ,  G10K2210/3044 ,  H04R2420/07 ,  H04R2460/01

Abstract: Techniques, apparatuses, and systems for wireless communication between proximate devices are disclosed. A first microphone on a first wearable audio device of a first user receives first audio signals that include speech from a second user proximate to the first user and ambient noise from an environment surrounding the first wearable audio device. The first audio signals are analyzed to determine primary audio directed to the first user. The primary audio is compared to other audio signals received through wireless communication channels between the first wearable audio device and one or more other wearable audio devices. In doing so, some of the other audio signals are determined to be similar to the primary audio and are thus output to the first wearable audio device. As a result, two users can accurately communicate, even in a noisy environment.

公开(公告)号：US20240072174A1

公开(公告)日：2024-02-29

申请号：US18237206

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Anthony J. Kanago ,  Haitao Liu ,  Si-Woo Lee ,  Soichi Sugiura

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/78615 ,  H01L29/78642 ,  H10B12/05 ,  H10B12/315

Abstract: A variety of applications can include an apparatus having an electronic device including a number of transistors in a pair-wise arrangement that can address a floating body effect associated with the type of transistor implemented in the pair-wise arrangement. The transistors can be structured as thin film transistors having one-gate separated by a gate dielectric from a vertical channel structure. The pair-wise arrangement can include a conductive shield between a channel structure of a transistor of the pair and a channel structure of the other transistor of the other pair. A conductive body can be located below the conductive shield and shorted to the conductive shield, where the conductive body contacts the channel structures of the transistors of the pair-wise arrangement. The conductive shield can be coupled to node to be set at a constant voltage in operation.

公开(公告)号：US20210358919A1

公开(公告)日：2021-11-18

申请号：US16874260

申请日：2020-05-14

Applicant: Micron Technology, Inc.

Inventor： Dojun Kim ,  Sanket S. Kelkar ,  Christopher W. Petz ,  Anthony J. Kanago ,  Brenda D. Kraus ,  Soichi Sugiura

IPC: H01L27/108 ,  H01L29/49 ,  H01L21/28 ,  C23C16/34 ,  C23C16/455 ,  C23C16/56 ,  C23C16/24

Abstract: Methods for forming microelectronic devices include forming a titanium nitride (TiN) material over a precursor structure. Forming the TiN material comprises repeating cycles of flowing a titanium-including gas adjacent the precursor structure; flowing a reducing gas over the precursor structure; flowing a nitrogen-including gas over the precursor structure; and, before and after flowing the nitrogen-including gas, purging gas. Related microelectronic device and related electronic systems are also described.