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    PRESERVING A DECOUPLING CAPACITOR'S CHARGE DURING LOW POWER OPERATION OF A LOGIC CIRCUIT
    1.
    发明公开
    PRESERVING A DECOUPLING CAPACITOR'S CHARGE DURING LOW POWER OPERATION OF A LOGIC CIRCUIT 审中-公开

    公开(公告)号：US20230393639A1

    公开(公告)日：2023-12-07

    申请号：US17805652

    申请日：2022-06-06

    Applicant: NXP B.V.

    Inventor： Andre Gunther ,  Jeffrey Alan Goswick ,  Rob Cosaro

    IPC: G06F1/3212 ,  G06F1/3296

    CPC classification number: G06F1/3212 ,  G06F1/3296

    Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

    Maximum voltage selector for power management applications
    2.
    发明授权
    Maximum voltage selector for power management applications 有权

    公开(公告)号：US11073857B1

    公开(公告)日：2021-07-27

    申请号：US17039926

    申请日：2020-09-30

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: H03K19/0185 ,  G05F1/575 ,  H03F3/45 ,  H03K19/20 ,  H03K17/687

    Abstract: A power supply switching circuit (100) and methodology are disclosed for connecting the greater of first and second power supplies (VSUP1, VSUP2) to an output voltage node (VOUT) with a comparator (102), active power supply switching circuit (103), gate driver circuit (106), and switching array (SW1-SW5) to generate control signals for a pair of PMOS power switches (MP1, MP2) by remapping first and second voltage supplies (VSUP1, VSUP2) to bias the n-wells of the PMOS power switches while simultaneously driving the gate terminals of the PMOS power switches with the gate driver circuit (106) only in response to a comparator activation signal by generating overlapping phase signals (PHI_1, PHI_2) which controls timing of first and second power supply selection signals so that a ground voltage is supplied as the first power supply selection signal only after the maximum bias voltage is supplied as the second power supply selection signal.

    Preserving a decoupling capacitor's charge during low power operation of a logic circuit
    3.
    发明授权
    Preserving a decoupling capacitor's charge during low power operation of a logic circuit 有权

    公开(公告)号：US12099394B2

    公开(公告)日：2024-09-24

    申请号：US17805652

    申请日：2022-06-06

    Applicant: NXP B.V.

    Inventor： Andre Gunther ,  Jeffrey Alan Goswick ,  Rob Cosaro

    IPC: G06F1/32 ,  G06F1/3212 ,  G06F1/3296

    CPC classification number: G06F1/3212 ,  G06F1/3296

    Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

    Active N-well switching circuit for power switches
    4.
    发明授权
    Active N-well switching circuit for power switches 有权

    公开(公告)号：US11424741B2

    公开(公告)日：2022-08-23

    申请号：US17039921

    申请日：2020-09-30

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: H03K17/687 ,  H03K17/567

    Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

    CIRCUITS AND METHODS FOR TRACKING MINIMUM VOLTAGE AT MULTIPLE SENSE POINTS
    6.
    发明申请
    CIRCUITS AND METHODS FOR TRACKING MINIMUM VOLTAGE AT MULTIPLE SENSE POINTS 有权

    公开(公告)号：US20220341975A1

    公开(公告)日：2022-10-27

    申请号：US17236227

    申请日：2021-04-21

    Applicant: NXP B.V.

    Inventor： Andre Luis Vilas Boas ,  Bruno Caceres Carrilho ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: G01R19/165 ,  H03K5/24 ,  H03K17/687 ,  G08B21/18

    Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.

    Active N-Well Switching Circuit for Power Switches
    7.
    发明申请
    Active N-Well Switching Circuit for Power Switches 有权

    公开(公告)号：US20220103170A1

    公开(公告)日：2022-03-31

    申请号：US17039921

    申请日：2020-09-30

    Applicant: NXP B.V.

    Inventor： Domenico Liberti ,  Andre Gunther ,  Jeffrey Alan Goswick

    IPC: H03K17/687 ,  H03K17/567

    Abstract: An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.

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