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    CLOCK DIAGNOSIS CIRCUIT
    1.
    发明申请
    CLOCK DIAGNOSIS CIRCUIT 失效
    时钟诊断电路

    公开(公告)号：US20130082739A1

    公开(公告)日：2013-04-04

    申请号：US13614235

    申请日：2012-09-13

    申请人： Naoya OHNISHI ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Makoto Toko

    发明人： Naoya OHNISHI ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Makoto Toko

    IPC分类号： G01R29/02

    CPC分类号： H03K5/19 ,  G06F1/04

    摘要： A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

    摘要翻译： 时钟诊断电路包括：将时钟延迟规定时间的延迟电路，该规定时间不大于时钟脉冲宽度; 整数乘法延迟电路，用于将从延迟电路输出的延迟时钟延迟预定数量的周期; 使用延迟时钟对时钟进行编码的第一异或电路; 使用积分乘法延迟电路的输出来对第一异或电路的输出进行解码的第二异或电路; 以及比较电路，用于将时钟与第二异或电路的输出进行比较，从而检测时钟的故障。

    Clock diagnosis circuit
    2.
    发明授权
    Clock diagnosis circuit 失效
    时钟诊断电路

    公开(公告)号：US08717066B2

    公开(公告)日：2014-05-06

    申请号：US13614235

    申请日：2012-09-13

    申请人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Makoto Toko

    发明人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Makoto Toko

    IPC分类号： H03K5/22

    CPC分类号： H03K5/19 ,  G06F1/04

    摘要： A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.

    摘要翻译： 时钟诊断电路包括：将时钟延迟规定时间的延迟电路，该规定时间不大于时钟脉冲宽度; 整数乘法延迟电路，用于将从延迟电路输出的延迟时钟延迟预定数量的周期; 使用延迟时钟对时钟进行编码的第一异或电路; 使用积分乘法延迟电路的输出来对第一异或电路的输出进行解码的第二异或电路; 以及比较电路，用于将时钟与第二异或电路的输出进行比较，从而检测时钟的故障。

    INFORMATION PROCESSING DEVICE EQUIPPED WITH WRITE-BACK CACHE AND DIAGNOSIS METHOD FOR MAIN MEMORY OF THE SAME
    3.
    发明申请
    INFORMATION PROCESSING DEVICE EQUIPPED WITH WRITE-BACK CACHE AND DIAGNOSIS METHOD FOR MAIN MEMORY OF THE SAME 失效
    装有回写速度的信息处理设备及其主要记忆的诊断方法

    公开(公告)号：US20120023374A1

    公开(公告)日：2012-01-26

    申请号：US13025499

    申请日：2011-02-11

    申请人： Naoya OHNISHI ,  Hiroshi Nakatani ,  Yoshito Sameda

    发明人： Naoya OHNISHI ,  Hiroshi Nakatani ,  Yoshito Sameda

    IPC分类号： G06F11/00

    CPC分类号： G11C29/44 ,  G06F12/0804 ,  G11C2029/0401 ,  G11C2029/0409

    摘要： The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.

    摘要翻译： 这些实施例提供了配备有回写高速缓存的信息处理设备中的主存储器的故障诊断方法。 根据该方法，将存储在主存储器中的应用程序除以回写高速缓存的存储大小，并且预先存储区域。 然后，检测从主存储器到写回高速缓存的读信号。 确定与读取信号相对应的区域是否尚未被诊断。 如果该地区尚未确诊，则会发出诊断该地区失败的指令。 如果在特定区域的诊断期间检测到特定区域的写入信号（回写），则特定区域的诊断被停止。 因此，与应用程序的执行并行地执行主存储器的故障诊断。

    Information processing device equipped with write-back cache and diagnosis method for main memory of the same
    4.
    发明授权
    Information processing device equipped with write-back cache and diagnosis method for main memory of the same 失效
    信息处理设备配备有回写缓存和主存储器的诊断方法

    公开(公告)号：US08516310B2

    公开(公告)日：2013-08-20

    申请号：US13025499

    申请日：2011-02-11

    申请人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda

    发明人： Naoya Ohnishi ,  Hiroshi Nakatani ,  Yoshito Sameda

    IPC分类号： G06F11/00

    CPC分类号： G11C29/44 ,  G06F12/0804 ,  G11C2029/0401 ,  G11C2029/0409

    摘要： The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.

    摘要翻译： 这些实施例提供了配备有回写高速缓存的信息处理设备中的主存储器的故障诊断方法。 根据该方法，将存储在主存储器中的应用程序除以回写高速缓存的存储大小，并且预先存储区域。 然后，检测从主存储器到写回高速缓存的读信号。 确定与读取信号相对应的区域是否尚未被诊断。 如果该地区尚未确诊，则会发出诊断该地区失败的指令。 如果在特定区域的诊断期间检测到特定区域的写入信号（回写），则特定区域的诊断被停止。 因此，与应用程序的执行并行地执行主存储器的故障诊断。

    PROCESSOR OPERATION MONITORING SYSTEM AND MONITORING METHOD THEREOF
    5.
    发明申请
    PROCESSOR OPERATION MONITORING SYSTEM AND MONITORING METHOD THEREOF 审中-公开
    处理器操作监控系统及其监控方法

    公开(公告)号：US20120185858A1

    公开(公告)日：2012-07-19

    申请号：US13349710

    申请日：2012-01-13

    申请人： Naoya OHNISHI ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Atsushi Inoue ,  Makoto Toko

    发明人： Naoya OHNISHI ,  Hiroshi Nakatani ,  Yoshito Sameda ,  Jun Takehara ,  Atsushi Inoue ,  Makoto Toko

    IPC分类号： G06F9/46

    CPC分类号： G06F11/0715 ,  G06F11/0721 ,  G06F11/076 ,  G06F11/20

    摘要： A processor includes a computation unit; a storage unit storing a program; and a data transmission circuit that transmits to an operation monitoring unit a signal corresponding to an instruction for reporting the execution stage of the program. The operation monitoring unit: includes a transition operation identification. circuit and a loop processing identification circuit. The transition operation identification circuit receives a start ID instruction with an attached ID that identifies a task; a termination ID instruction that identifies termination of task operation; and if the task is execution of loop processing, a loop instruction that reports the maximum value of the number of times of this loop processing. The transition operation identification circuit identifies success of the transition operations of the tasks of the program, based on the ID instructions. The loop processing identification circuit identifies abnormality of the number of times of loop processing.

    摘要翻译： 处理器包括计算单元; 存储单元，存储程序; 以及数据传输电路，向操作监视单元发送与用于报告程序的执行阶段的指令相对应的信号。 操作监视单元包括过渡操作标识。 电路和环路处理识别电路。 转移操作识别电路接收具有识别任务的附加ID的开始ID指令; 终止ID指令，用于标识任务操作的终止; 并且如果任务是执行循环处理，则循环指令报告该循环处理的次数的最大值。 过渡操作识别电路基于ID指令来识别程序的任务的转换操作的成功。 循环处理识别电路识别循环处理次数的异常。

    Capacitative electromagnetic flow meter
    7.
    发明授权
    Capacitative electromagnetic flow meter 有权
    电容式电磁流量计

    公开(公告)号：US06802223B2

    公开(公告)日：2004-10-12

    申请号：US10669565

    申请日：2003-09-25

    申请人： Hiroshi Nakatani ,  Tatsuya Kimura ,  Yoshito Sameda ,  Takuya Iijima ,  Takashi Higuchi ,  Makoto Futoo ,  Hiroaki Nojiri ,  Kiyonori Nishikawa ,  Toshihiko Okamoto

    发明人： Hiroshi Nakatani ,  Tatsuya Kimura ,  Yoshito Sameda ,  Takuya Iijima ,  Takashi Higuchi ,  Makoto Futoo ,  Hiroaki Nojiri ,  Kiyonori Nishikawa ,  Toshihiko Okamoto

    IPC分类号： G01F158

    CPC分类号： G01F1/584 ,  G01F1/586

    摘要： The invention consists in a capacitative electromagnetic flow meter in which excitation is performed at a frequency above the commercially available frequency and having a characteristic correction filter that corrects the gain frequency characteristic of the exciting current such that the exciting flux waveform has a flat section. In the detection unit, the value of the electrostatic capacitance between the face electrodes 4A, 4B and guard electrodes 5A, 5B is made smaller than the value of the electrostatic capacitance between the detecting face electrodes 4A, 4B and the fluid to be measured. The exciting coils are fixed to a cylindrical yoke, being electrostatically screened by coil fixing plates. Fixing by an earth ring is performed with this cylindrical yoke and the two ends of the measurement tube being symmetrical with respect to the tube axis and electrode axes. In addition, fixing is effected by filling the entire interior of the detection unit with epoxy resin.

    摘要翻译： 本发明是一种电容式电磁流量计，其中以高于市售频率的频率进行激励，并且具有校正激励电流的增益频率特性的特征校正滤波器，使得激励磁通波形具有平坦部分。 在检测单元中，使面电极4A，4B与保护电极5A，5B之间的静电电容值小于检测面电极4A，4B与待测流体之间的静电电容值。 励磁线圈固定到圆柱形轭，由线圈固定板静电屏蔽。 用该圆柱形磁轭进行固定，测量管的两端相对于管轴和电极轴对称。 此外，通过用环氧树脂填充检测单元的整个内部来实现固定。

    INDUSTRIAL CONTROLLER
    8.
    发明申请
    INDUSTRIAL CONTROLLER 有权
    工业控制器

    公开(公告)号：US20080281896A1

    公开(公告)日：2008-11-13

    申请号：US12108774

    申请日：2008-04-24

    申请人： Yoshito SAMEDA ,  Hiroshi Nakatani ,  Akira Sawada ,  Jun Takehara ,  Hiroyuki Nishikawa ,  Motohiko Okabe

    发明人： Yoshito SAMEDA ,  Hiroshi Nakatani ,  Akira Sawada ,  Jun Takehara ,  Hiroyuki Nishikawa ,  Motohiko Okabe

    IPC分类号： G06F7/48

    CPC分类号： H04L9/008 ,  G06F11/085

    摘要： A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (13), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder (11c) for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.

    摘要翻译： 第一算术运算器（11）包括：第一模数算术编码编码器（11b），用于将通过中央控制器（31）的命令发送的数值数据编码为模数运算代码;第一算术运算处理器（11a），使用 将作为输入操作数编码的模数算术的数值数据作为基于来自中央控制器（13）的命令执行算术运算，提供模数运算代码形式的输出和第一模运算代码解码器（ 11c）用于确定从第一算术运算处理器输出的数值数据中存在或不存在位错误，如果检测到的话，校正位错误，以输出解码的数字数据。

    Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line
    10.
    发明授权
    Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line 有权
    总线信号控制电路，用于使用单独的总线诊断线检测总线信号异常

    公开(公告)号：US08131900B2

    公开(公告)日：2012-03-06

    申请号：US12432896

    申请日：2009-04-30

    申请人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

    发明人： Jun Takehara ,  Naruhiko Aramaki ,  Toshikazu Kawamura ,  Yoshito Sameda ,  Hiroshi Nakatani ,  Motohiko Okabe ,  Yukitaka Yoshida

    IPC分类号： G06F13/00 ,  H04L1/14

    CPC分类号： G06F11/0793 ,  G06F11/0745

    摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

    摘要翻译： 存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。 总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。 总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。 当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。