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公开(公告)号：US6049897A
公开(公告)日：2000-04-11
申请号：US779791
申请日：1997-01-07
CPC分类号： G06F12/1441
摘要： A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.
摘要翻译： 在存储器访问期间，使用新的方法和装置来检查段限制违规。 当在段的初始化期间检索到段描述符时，段描述符的段限制用于创建五个限制。 五个限制是每个内存访问大小的段内最后一个可能的地址。 在随后的存储器访问期间，选择与被访问的段相对应的限制和存储器访问的长度。 将选定的限制与存储器访问的地址进行比较，以确定是否发生了限制冲突。 如果发生限制违规，则会设置一个标志，当读取时会引发异常。
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公开(公告)号：US6055652A
公开(公告)日：2000-04-25
申请号：US314439
申请日：1999-05-19
CPC分类号： G06F12/1441
摘要： A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.
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3.发明授权公开(公告)号：US07062636B2
公开(公告)日：2006-06-13
申请号：US10247894
申请日：2002-09-19
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3859
摘要： Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine The issue engine categorizes operations as at least one of either a speculative operation, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.
摘要翻译： 实施例包括各种方法，装置和系统，其中处理器包括乱序发布引擎和顺序执行流水线。 对于一些实施例，问题引擎可能远离执行流水线，并且执行资源可能距离问题引擎许多时钟周期。问题引擎将操作归类为执行计算的推测操作或建筑操作中的至少一个 有可能出现故障或引起例外。 潜在的除外操作可以分解成两个单独的微操作：推测微操作，其用于推测性地生成数据结果，以便可以推测地发布依赖于结果的操作，以及建筑微操作，其指示故障 除外操作的条件。 存储操作成为架构操作，并且可以保证所有以前的故障条件在发布存储之前进行评估。
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4.发明授权公开(公告)号：US07392369B2
公开(公告)日：2008-06-24
申请号：US11406879
申请日：2006-04-18
IPC分类号： G06F9/312
CPC分类号： G06F9/3834 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3859
摘要： Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine. The issue engine categorizes operations as at least one of either a speculative operations which perform computations, or an architectural operations which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.
摘要翻译： 实施例包括各种方法，装置和系统，其中处理器包括乱序发布引擎和顺序执行流水线。 对于一些实施例，问题引擎可能远离执行流水线，并且执行资源可能距离问题引擎很多时钟周期。 问题引擎将操作分类为执行计算的推测操作或具有故障或引起异常的可能性的架构操作中的至少一个。 潜在的除外操作可以分解成两个单独的微操作：推测微操作，其用于推测性地生成数据结果，以便可以推测地发布依赖于结果的操作，以及建筑微操作，其指示故障 除外操作的条件。 存储操作成为架构操作，并且可以保证所有以前的故障条件在发布存储之前进行评估。
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5.发明授权Resolving all previous potentially excepting architectural operations before issuing store architectural operation 失效在发布商店架构操作之前解决所有以前的潜在的除架构操作公开(公告)号：US07330963B2
公开(公告)日：2008-02-12
申请号：US11407183
申请日：2006-04-18
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/3017 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3859
摘要： Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may be many clock cycles away from the issue engine. The issue engine categorizes operations as at least one of either a speculative operations, which perform computations, or an architectural operation, which has potential to fault or cause an exception. Potentially excepting operations may be decomposed into two separate micro-operations: a speculative micro-operation, which is used to generate data results speculatively so that operations dependent on the results may be speculatively issued, and an architectural micro-operation, which signals the faulting condition for the excepting operation. A STORE operation becomes an architectural operation and all previous faulting conditions may be guaranteed to have evaluated before a STORE is issued.
摘要翻译： 实施例包括各种方法，装置和系统，其中处理器包括乱序发布引擎和顺序执行流水线。 对于一些实施例，问题引擎可能远离执行流水线，并且执行资源可能距离问题引擎很多时钟周期。 问题引擎将操作分类为执行计算的推测操作或具有故障或引起异常的可能性的架构操作中的至少一个。 潜在的除外操作可以分解成两个单独的微操作：推测微操作，其用于推测性地生成数据结果，以便可以推测地发布依赖于结果的操作，以及建筑微操作，其指示故障 除外操作的条件。 存储操作成为架构操作，并且可以保证所有以前的故障条件在发布存储之前进行评估。
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公开(公告)号：US06393544B1
公开(公告)日：2002-05-21
申请号：US09430793
申请日：1999-10-31
申请人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , James O. Hays , Jerome C. Huck , Jonathan K. Ross , Sunil Saxena , Koichi Yamada
发明人： William R. Bryg , Stephen G. Burger , Gary N. Hammond , James O. Hays , Jerome C. Huck , Jonathan K. Ross , Sunil Saxena , Koichi Yamada
IPC分类号： G06F1200
CPC分类号： G06F12/1018 , G06F2212/652
摘要： A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2K bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2L bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.
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7.发明授权Computer architecture for the deferral of exceptions on speculative instructions 失效计算机架构，用于推测投机说明上的例外
公开(公告)号：US5915117A
公开(公告)日：1999-06-22
申请号：US949295
申请日：1997-10-13
申请人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
发明人： Jonathan K. Ross , Jack D. Mills , James O. Hays , Stephen G. Burger , Dale C. Morris , Carol L. Thompson , Rajiv Gupta , Stefan M. Freudenberger , Gary N. Hammond , Ralph M. Kling
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3842
摘要： The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.
摘要翻译： 本发明的系统和方法允许软件控制在推测操作中硬件推迟异常，并且包括三个组件。 第一个组件是反映应用程序的代码生成策略的处理器存储信息，由硬件和操作系统用来控制异常延期。 第二个组件是由操作系统设置的处理器存储信息，用于指定硬件哪种类型的故障应该自动延迟。 第三组件是进一步处理器存储的信息，其指示硬件推迟导致投机操作方面的某些异常，同时执行投机操作的其他非例外方面。 存储的信息在操作系统异常处理程序未成功尝试故障解决之后进行设置。
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8.发明申请Performance In A Virtualization Architecture With A Processor Abstraction Layer 审中-公开在具有处理器抽象层的虚拟化架构中的性能公开(公告)号：US20120240116A1
公开(公告)日：2012-09-20
申请号：US13483307
申请日：2012-05-30
申请人： Hin L. Leung , Amy L. Santoni , Gary N. Hammond , William R. Greene , Kushagra V. Vaid , Dale Morris , Jonathan Ross
发明人： Hin L. Leung , Amy L. Santoni , Gary N. Hammond , William R. Greene , Kushagra V. Vaid , Dale Morris , Jonathan Ross
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.
摘要翻译： 公开了用于提高虚拟化架构中的性能的装置和方法的实施例。 在一个实施例中，一种装置包括处理器和处理器抽象层。 处理器抽象层包括当由处理器执行时支持技术来提高虚拟化架构中的设备的性能的指令。
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9.发明授权Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address 失效使用至少一种默认页面大小和为虚拟地址空间选择的页面大小之一的页表步行器将滑动字段放置在虚拟地址中
公开(公告)号：US06088780A
公开(公告)日：2000-07-11
申请号：US829337
申请日：1997-03-31
申请人： Koichi Yamada , Gary N. Hammond , Jim Hays , Jonathan Kent Ross , Stephen Burger , William R. Bryg
发明人： Koichi Yamada , Gary N. Hammond , Jim Hays , Jonathan Kent Ross , Stephen Burger , William R. Bryg
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.
摘要翻译： 一种用于实现使用为虚拟地址空间选择的默认页面大小和页面大小中的至少一个来定位虚拟地址中的滑动字段的页表行进者的方法和装置。 根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其包括页面大小存储区域和页表行进器。 页面大小存储区域用于存储每个被选择用于翻译不同虚拟地址集合的页面大小的数量。 页表步行器包括耦合到页面大小存储区域的选择单元以及耦合到选择单元的页面输入地址生成器。 对于接收到的每个虚拟地址，选择单元基于为了翻译该虚拟地址所属的虚拟地址集而选择的页面大小来定位该虚拟地址中的字段。 响应于接收到为每个虚拟地址标识的字段中的比特，页面入口地址生成器基于这些比特识别页表中的条目。
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10.发明授权Method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table 失效用于实现页表行进者的方法和装置，其使用虚拟地址中的滑动字段来识别页表中的条目
公开(公告)号：US6012132A
公开(公告)日：2000-01-04
申请号：US829782
申请日：1997-03-31
申请人： Koichi Yamada , Gary N. Hammond
发明人： Koichi Yamada , Gary N. Hammond
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： A method and apparatus for implementing a page table walker that uses a sliding field in the virtual addresses to identify entries in a page table. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes selected for translating a number of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each virtual address received by the selection unit, the selection unit positions a field in that virtual address based on the page size selected for translating that virtual address. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.
摘要翻译： 一种用于实现使用虚拟地址中的滑动字段来识别页表中的条目的页表行进器的方法和装置。 根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其包括页面大小存储区域和页表行进器。 页面大小存储区域用于存储选择用于翻译多个虚拟地址的多个页面大小。 页表步行器包括耦合到页面大小存储区域的选择单元以及耦合到选择单元的页面输入地址生成器。 对于由选择单元接收的每个虚拟地址，选择单元基于为了翻译该虚拟地址而选择的页面大小来定位该虚拟地址中的字段。 响应于接收到为每个虚拟地址标识的字段中的比特，页面入口地址生成器基于这些比特识别页表中的条目。
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