公开(公告)号：US10999107B1

公开(公告)日：2021-05-04

申请号：US16946250

申请日：2020-06-12

Applicant: Novatek Microelectronics Corp.

Inventor： Shih-Chun Lin ,  Ming-Hung Chien ,  Shu-Chin Chuang

IPC: H04L25/02 ,  H04L25/03

Abstract: A voltage mode transmitter includes a first output terminal, a second output terminal, and a plurality switch-resistor units between the first output terminal and a first voltage source, between the second output terminal and the first voltage source, between the first output terminal and a second voltage source, and between the second output terminal and the second voltage source. Each switch-resistor unit includes a switch and a resistor connected in series. The switches of the switch-resistor units are controlled such that a common-mode voltage of a differential signal outputted at the first and second output terminals deviates from an average of voltages provided by the first and second voltage sources.

公开(公告)号：US11863149B2

公开(公告)日：2024-01-02

申请号：US17707991

申请日：2022-03-30

Applicant: Novatek Microelectronics Corp.

Inventor： Shu-Chin Chuang ,  Shih-Chun Lin ,  Ming-Hung Chien

IPC: H03H11/28

CPC classification number: H03H11/28

Abstract: A signal transmitter includes a plurality of driver slices. Each of the driver slices includes a driving circuit, a plurality of first transistors, and a plurality of second transistors. The driving circuit receives an input signal and outputting an output signal. The first transistors provide a first impedance according to signals on gate terminals of the first transistors. The second transistors provide a second impedance according to signals on gate terminals of the second transistors. Each of the gate terminals of the first transistors and the second transistors is selectively coupled to a bias voltage which controls the corresponding first transistor or second transistor to operate in a triode region, or coupled to a predetermined voltage which controls the corresponding first transistor or second transistor to behave as a switch.

公开(公告)号：US20170279461A1

公开(公告)日：2017-09-28

申请号：US15409478

申请日：2017-01-18

Applicant: Novatek Microelectronics Corp.

Inventor： Shih-Chun Lin ,  Ren-Hong Luo ,  Mu-Jung Chen ,  Yung-Cheng Lin

IPC: H03M9/00 ,  H03K3/037 ,  H03K5/01

CPC classification number: H03M9/00 ,  H03K3/037 ,  H03K5/01 ,  H03K5/15046 ,  H03K2005/00019

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

公开(公告)号：US20230318578A1

公开(公告)日：2023-10-05

申请号：US17707991

申请日：2022-03-30

Applicant: Novatek Microelectronics Corp.

Inventor： Shu-Chin Chuang ,  Shih-Chun Lin ,  Ming-Hung Chien

IPC: H03H11/28

CPC classification number: H03H11/28

Abstract: A signal transmitter includes a plurality of driver slices. Each of the driver slices includes a driving circuit, a plurality of first transistors, and a plurality of second transistors. The driving circuit receives an input signal and outputting an output signal. The first transistors provide a first impedance according to signals on gate terminals of the first transistors. The second transistors provide a second impedance according to signals on gate terminals of the second transistors. Each of the gate terminals of the first transistors and the second transistors is selectively coupled to a bias voltage which controls the corresponding first transistor or second transistor to operate in a triode region, or coupled to a predetermined voltage which controls the corresponding first transistor or second transistor to behave as a switch.

公开(公告)号：US09800265B2

公开(公告)日：2017-10-24

申请号：US15409478

申请日：2017-01-18

Applicant: Novatek Microelectronics Corp.

Inventor： Shih-Chun Lin ,  Ren-Hong Luo ,  Mu-Jung Chen ,  Yung-Cheng Lin

IPC: H03M9/00 ,  H03K5/01 ,  H03K3/037 ,  H03K5/00

CPC classification number: H03M9/00 ,  H03K3/037 ,  H03K5/01 ,  H03K5/15046 ,  H03K2005/00019

Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.