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公开(公告)号：US20170279461A1
公开(公告)日：2017-09-28
申请号：US15409478
申请日：2017-01-18
Applicant: Novatek Microelectronics Corp.
Inventor： Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC classification number: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
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2.发明授权公开(公告)号：US09515699B2
公开(公告)日：2016-12-06
申请号：US14723449
申请日：2015-05-27
Applicant: Novatek Microelectronics Corp.
Inventor： Ren-Hong Luo , Yan-Ting Wang , Hsiang-Chi Li , Mu-Jung Chen
Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.
Abstract translation: 提供了一种用于切换其模式的双模串行传输装置和方法。 双模串行传输装置包括第一和第二电流源，第一和第二反相电路，差分对和电阻串。 第一反相电路接收模式选择信号或第一数据传输信号，第二反相电路接收模式选择信号或第二数据传输信号。 差分对的第一和第二负载端子分别耦合到第一和第二反相电路。 差分对的公共端耦合到第二电流源。 第一和第二差分输入端子接收模式选择信号或分别接收第一和第二数据传输信号。 电阻串串联在第一和第二反相电路的输出端之间。
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Patent Agency Ranking
3.发明申请公开(公告)号：US20160226557A1
公开(公告)日：2016-08-04
申请号：US14723449
申请日：2015-05-27
Applicant: Novatek Microelectronics Corp.
Inventor： Ren-Hong Luo , Yan-Ting Wang , Hsiang-Chi Li , Mu-Jung Chen
Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.
Abstract translation: 提供了一种用于切换其模式的双模串行传输装置和方法。 双模串行传输装置包括第一和第二电流源，第一和第二反相电路，差分对和电阻串。 第一反相电路接收模式选择信号或第一数据传输信号，第二反相电路接收模式选择信号或第二数据传输信号。 差分对的第一和第二负载端子分别耦合到第一和第二反相电路。 差分对的公共端耦合到第二电流源。 第一和第二差分输入端子接收模式选择信号或分别接收第一和第二数据传输信号。 电阻串串联在第一和第二反相电路的输出端之间。
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公开(公告)号：US09929741B1
公开(公告)日：2018-03-27
申请号：US15354989
申请日：2016-11-17
Applicant: NOVATEK Microelectronics Corp.
Inventor： Chu-Wei Hsia , Mu-Jung Chen
IPC: H03M1/66
CPC classification number: H03M1/742
Abstract: A control circuit for a current switch of a current digital to analog converter (DAC) includes a first inverter, a second inverter, a first pull-low switch, a second pull-low switch and a timing synchronization circuit. The first inverter includes an input terminal and an output terminal. The second inverter includes an input terminal and an output terminal, wherein the input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter is coupled to the input terminal of the first inverter. The first pull-low switch is coupled to the input terminal of the first inverter. The second pull-low switch is coupled to the input terminal of the second inverter. The timing synchronization circuit is coupled to the first pull-low switch and the second pull-low switch.
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公开(公告)号：US10606294B1
公开(公告)日：2020-03-31
申请号：US16240778
申请日：2019-01-06
Applicant: NOVATEK Microelectronics Corp.
Inventor： Liang-Ting Kuo , Mu-Jung Chen , Chi-Chun Liao
Abstract: A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.
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公开(公告)号：US09948279B1
公开(公告)日：2018-04-17
申请号：US15473602
申请日：2017-03-29
Applicant: NOVATEK Microelectronics Corp.
Inventor： Mu-Jung Chen , Nan-Yuan Wang
IPC: H03K17/16 , H03K19/003 , H03H11/12 , H03H11/30
CPC classification number: H03H7/38 , H03H11/126 , H03H2210/012 , H03H2210/025 , H03H2210/028
Abstract: An electronic device capable of bandwidth compensation includes a register unit for storing a calibration code determined by performing an on-die termination (ODT) calibration process and a data receiving circuit, wherein the calibration code is utilized for controlling a termination resistance of an ODT unit. The data receiving circuit comprises a first control circuit coupled to the register unit and the active low-pass filter for generating a first control signal according to the calibration code stored in the register unit, the first control signal being utilized for adjusting a capacitance of a first feedback capacitor unit or a resistance of a first feedback resistor unit of an active low-pass filter.
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公开(公告)号：US09800265B2
公开(公告)日：2017-10-24
申请号：US15409478
申请日：2017-01-18
Applicant: Novatek Microelectronics Corp.
Inventor： Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC classification number: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
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