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公开(公告)号：US20170279461A1
公开(公告)日：2017-09-28
申请号：US15409478
申请日：2017-01-18
Applicant: Novatek Microelectronics Corp.
Inventor： Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC classification number: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
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2.发明公开公开(公告)号：US20230290715A1
公开(公告)日：2023-09-14
申请号：US17990727
申请日：2022-11-20
Applicant: NOVATEK Microelectronics Corp.
Inventor： Tsung-Ling Li , Yung-Cheng Lin , Ju-Lin Huang
IPC: H01L23/498 , G06F3/041 , G06F3/044
CPC classification number: H01L23/49838 , H01L23/49816 , G06F3/04164 , G06F3/0412 , G06F3/0446
Abstract: A ball grid array (BGA) package for use in a touch panel controller includes a package substrate and a plurality of solder bumps. The plurality of solder bumps are disposed on the package substrate, arranged in a staggered pattern surrounding a hollow region on the package substrate, and coupled to electrodes of a touch panel via a multi-layer circuit board. The staggered pattern includes Ys1 top rows and Ys2 bottom rows, a minimum vertical distance between centers of two vertically adjacent solder bumps in the Ys1 top rows and the Ys2 bottom rows being referred to as an equivalent vertical pitch, and Ys1, Ys2 being integers exceeding 2. the hollow region has a minimum length defined by the minimum length=((Ys1−2)+(Ys2−2))*the equivalent vertical pitch.
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公开(公告)号：US11196425B1
公开(公告)日：2021-12-07
申请号：US16996876
申请日：2020-08-18
Applicant: NOVATEK Microelectronics Corp.
Inventor： Che-Yi Lin , Yung-Cheng Lin
Abstract: An eye width monitor (EWM) for a clock and data recovery (CDR) circuit includes a delay circuit, a first multiplexer (MUX) and a calibration circuit. The delay circuit includes an input terminal and an output terminal. The first MUX, coupled to the delay circuit, includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first MUX is coupled to a clock input terminal of the EWM. The second input terminal of the first MUX is coupled to the output terminal of the delay circuit. The output terminal of the first MUX is coupled to the input terminal of the delay circuit. The calibration circuit, coupled to the delay circuit, is configured to receive an oscillation clock from the delay circuit and receive a reference clock, and calibrate the oscillation clock with the reference clock.
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公开(公告)号：US09800265B2
公开(公告)日：2017-10-24
申请号：US15409478
申请日：2017-01-18
Applicant: Novatek Microelectronics Corp.
Inventor： Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC classification number: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
Abstract: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
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