-
1.发明公开公开(公告)号：US20240312881A1
公开(公告)日：2024-09-19
申请号：US18674329
申请日：2024-05-24
发明人： Toshifumi ISHIDA , Kouki YAMAMOTO
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49562 , H01L24/16 , H01L24/40 , H01L24/73 , H01L2224/16227 , H01L2224/40245 , H01L2224/73255
摘要： A power storage pack includes: a power storage cell; a power storage tab; a protection circuit substrate; a semiconductor element; and a metal plate for power storage tab joint that is connected to the semiconductor element on the first main surface of the metal plate for power storage tab joint and that includes a portion whose thickness is at most 0.2 mm. The metal plate for power storage tab joint is joined to the power storage tab on the second main surface of the metal plate for power storage tab joint to include an overlap portion in which the power storage tab, the metal plate for power storage tab joint, the semiconductor element, and the protection circuit substrate overlap each other; and there is a portion in which a region that may be the conduction path between the power storage tab and the protection circuit substrate overlaps the overlap portion.
-
公开(公告)号：US20220337029A1
公开(公告)日：2022-10-20
申请号：US17854921
申请日：2022-06-30
IPC分类号： H01S5/042 , H01L23/00 , H01S5/0236 , H01S5/02345 , G01S7/481
摘要： A semiconductor device of a hybrid type includes: a light-emitting element forming a power loop; a semiconductor integrated circuit element including a switching element; and a bypass capacitor. The light-emitting element and the switching element constitute a layered body in which respective principal surfaces of the light-emitting element and the switching element are layered in parallel and face-to-face. The bypass capacitor includes one electrode connected to a lower element of the layered body, and an other electrode connected to an upper element of the layered body. In a plan view, when a direction from the one electrode to the other electrode inside the bypass capacitor is a first direction, the bypass capacitor is arranged so that a side of the bypass capacitor parallel to the first direction includes a portion that is parallel to and faces one peripheral side of the layered body.
-
公开(公告)号：US20230307393A1
公开(公告)日：2023-09-28
申请号：US18044746
申请日：2022-02-10
IPC分类号： H01L23/00 , H01L29/78 , H01L25/065
CPC分类号： H01L24/06 , H01L24/08 , H01L25/0655 , H01L29/7813 , H01L2224/06152 , H01L2224/08225
摘要： A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.
-
公开(公告)号：US20230215940A1
公开(公告)日：2023-07-06
申请号：US18181332
申请日：2023-03-09
发明人： Kouki YAMAMOTO , Haruhisa TAKATA
IPC分类号： H01L29/78 , H01L27/088 , H02J7/00 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7802 , H01L27/088 , H02J7/0029 , H01L29/41725 , H01L29/4232
摘要： A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.
-
公开(公告)号：US20240030167A1
公开(公告)日：2024-01-25
申请号：US18477224
申请日：2023-09-28
IPC分类号： H01L23/00 , H01L25/065 , H01L29/78
CPC分类号： H01L24/06 , H01L24/08 , H01L25/0655 , H01L29/7813 , H01L2224/06152 , H01L2224/08225
摘要： A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.
-
公开(公告)号：US20220020658A1
公开(公告)日：2022-01-20
申请号：US17486313
申请日：2021-09-27
摘要： A power amplification device includes: a first semiconductor chip including a first main surface and a second main surface; a first field-effect transistor, a first drain finger part, a plurality of first gate finger parts, and a source finger part; a sub-mount substrate including a third main surface and a fourth main surface; and a first filled via provided penetrating from the third main surface to the fourth main surface. In plan view, the first filled via has a rectangular shape. A long side direction of the first filled via is parallel to a long side direction of the plurality of first gate finger parts. In plan view, the first filled via is positioned to overlap part of one first gate finger part included in the plurality of first gate finger parts.
-
公开(公告)号：US20230317841A1
公开(公告)日：2023-10-05
申请号：US18330053
申请日：2023-06-06
发明人： Kouki YAMAMOTO , Haruhisa TAKATA
IPC分类号： H02J7/00 , H01L29/78 , H01L27/088 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7802 , H01L27/088 , H01L29/41725 , H01L29/4232 , H02J7/0029
摘要： A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.016 秒)
