公开(公告)号：US09355211B2

公开(公告)日：2016-05-31

申请号：US14511283

申请日：2014-10-10

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Yibin Xia ,  Dinesh Rajasavari Amirtharaj ,  Ali Vahidsafa ,  Alan Smith ,  Senthilkumar Diraviam ,  Mohd Jamil Mohd

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Abstract translation: 描述了与提供用于执行电路设计的设计约束生成和验证的统一工具相关联的系统，方法和其它实施例。 在一个实施例中，统一工具读取用于电路设计的设计数据和设计意图信息。 统一的工具至少部分地基于设计数据和设计意图信息，一起并相互依赖地生成电路设计的物理流程元素和验证流程元素。

公开(公告)号：US10656205B2

公开(公告)日：2020-05-19

申请号：US15886566

申请日：2018-02-01

Applicant: Oracle International Corporation

Inventor： Mark Semmelmeyer ,  Ali Vahidsafa ,  Sebastian Turullols ,  Scott Cooke ,  Senthilkumar Diraviam ,  Preethi Sama

IPC: G01R31/3183 ,  G01R31/28 ,  G01R31/319 ,  G01R31/317

Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.