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    Integrated magnetic field generation and detection platform
    1.
    发明授权
    Integrated magnetic field generation and detection platform 有权
    集成磁场发生和检测平台

    公开(公告)号：US08614572B2

    公开(公告)日：2013-12-24

    申请号：US12837429

    申请日：2010-07-15

    申请人： Octavian Florescu ,  Bernhard E. Boser ,  Moritz Mattmann

    发明人： Octavian Florescu ,  Bernhard E. Boser ,  Moritz Mattmann

    IPC分类号： G01R33/06

    CPC分类号： G01N33/5438 ,  G01N33/54326 ,  G01R33/1269

    摘要： An integrated magnetic field generation and detection platform is described that is capable of manipulating and detecting individual magnetic particles, such as spherical super-paramagnetic beads, and providing biosensing functionality. The platform is implemented in an integrated circuit, a portion of the surface of which is functionalized with one or more biochemical agents that binds tightly (i.e., specifically) with a target analyte. The magnetic beads are similarly functionalized with one or more biochemical agents that that bind specifically with the target analyte. When a sample is introduced, magnetic beads that specifically bind to the integrated circuit can be separated from non-specifically bound beads and detected.

    摘要翻译： 描述了能够操纵和检测诸如球形超顺磁珠的各个磁性颗粒并提供生物传感功能的集成磁场产生和检测平台。 该平台在集成电路中实施，其表面的一部分由与靶分析物紧密（即具体地）结合的一种或多种生化试剂功能化。 磁珠类似地与一种或多种与靶分析物特异性结合的生物化学试剂官能化。 当引入样品时，特异性结合集成电路的磁珠可以与非特异性结合的珠分离并检测。

    INTEGRATED MAGNETIC FIELD GENERATION AND DETECTION PLATFORM
    2.
    发明申请
    INTEGRATED MAGNETIC FIELD GENERATION AND DETECTION PLATFORM 有权
    集成磁场产生与检测平台

    公开(公告)号：US20110018532A1

    公开(公告)日：2011-01-27

    申请号：US12837429

    申请日：2010-07-15

    申请人： Octavian Florescu ,  Bernhard E. Boser ,  Moritz Mattmann

    发明人： Octavian Florescu ,  Bernhard E. Boser ,  Moritz Mattmann

    IPC分类号： G01R33/06

    CPC分类号： G01N33/5438 ,  G01N33/54326 ,  G01R33/1269

    摘要： An integrated magnetic field generation and detection platform is described that is capable of manipulating and detecting individual magnetic particles, such as spherical super-paramagnetic beads, and providing biosensing functionality. The platform is implemented in an integrated circuit, a portion of the surface of which is functionalized with one or more biochemical agents that binds tightly (i.e., specifically) with a target analyte. The magnetic beads are similarly functionalized with one or more biochemical agents that that bind specifically with the target analyte. When a sample is introduced, magnetic beads that specifically bind to the integrated circuit can be separated from non-specifically bound beads and detected.

    摘要翻译： 描述了能够操纵和检测诸如球形超顺磁珠的各个磁性颗粒并提供生物传感功能的集成磁场产生和检测平台。 该平台在集成电路中实施，其表面的一部分由与靶分析物紧密（即具体地）结合的一种或多种生化试剂功能化。 磁珠类似地与一种或多种与靶分析物特异性结合的生化试剂功能化。 当引入样品时，特异性结合集成电路的磁珠可以与非特异性结合的珠分离并检测。

    PLL lock management system
    3.
    发明授权
    PLL lock management system 有权
    PLL锁定管理系统

    公开(公告)号：US07323944B2

    公开(公告)日：2008-01-29

    申请号：US11103743

    申请日：2005-04-11

    申请人： Octavian Florescu ,  Amr M. Fahim ,  Chiewcharn Narathong

    发明人： Octavian Florescu ,  Amr M. Fahim ,  Chiewcharn Narathong

    IPC分类号： H03L7/06 ,  H03L7/10

    CPC分类号： H03L7/199 ,  H03L7/0898 ,  H03L7/10

    摘要： A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

    摘要翻译： PLL包括电荷泵，环路滤波器，VCO和校准单元。 校准单元执行粗调以选择一个或多个频率范围，执行微调以确定将VCO置于所需工作频率附近的初始控制电压，测量不同控制电压下的VCO增益，并导出VCO增益补偿值 不同的控制电压。 校准单元还将环路滤波器预充电到初始控制电压以缩短采集时间，使环路滤波器能够驱动VCO锁定到所需的工作频率，并在正常操作期间执行VCO增益补偿。 对于VCO增益补偿，校准单元测量控制电压，获得测量的控制电压的VCO增益补偿值，并调整至少一个电路块（例如，电荷泵）的增益，以考虑VCO增益的变化 。

    Low-leakage current sources and active circuits
    5.
    发明授权
    Low-leakage current sources and active circuits 有权
    低漏电流源和有源电路

    公开(公告)号：US07551021B2

    公开(公告)日：2009-06-23

    申请号：US11165269

    申请日：2005-06-22

    申请人： Octavian Florescu

    发明人： Octavian Florescu

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262 ,  G05F1/575

    摘要： A low-leakage circuit includes first, second, and third transistors, which may be P-channel or N-channel FETs. The first transistor provides an output current when enabled and presents low leakage current when disabled. The second transistor enables or disables the first transistor. The third transistor connects or isolates the first transistor to/from a predetermined voltage (e.g., VDD or VSS). The circuit may further include a pass transistor that provides a reference voltage to the source of the first transistor when the first transistor is disabled. In an ON state, the first transistor provides the output current, and the second and third transistors do not impact performance. In an OFF state, the second and third transistors are used to provide appropriate voltages to the first transistor to place it in a low-leakage state. The first, second, and third transistors may be used for a low-leakage current source within a current mirror, an amplifier stage, and so on.

    摘要翻译： 低泄漏电路包括第一，第二和第三晶体管，其可以是P沟道或N沟道FET。 第一个晶体管在使能时提供输出电流，并在禁用时呈现低泄漏电流。 第二晶体管启用或禁用第一晶体管。 第三晶体管将第一晶体管连接或隔离预定电压（例如，VDD或VSS）。 电路还可以包括传输晶体管，当第一晶体管被禁用时，该传输晶体管向第一晶体管的源极提供参考电压。 在导通状态下，第一晶体管提供输出电流，第二和第三晶体管不影响性能。 在OFF状态下，第二和第三晶体管用于向第一晶体管提供适当的电压以将其置于低泄漏状态。 第一，第二和第三晶体管可以用于电流镜，放大器级等内的低泄漏电流源。

    Delay matching for clock distribution in a logic circuit
    6.
    发明授权
    Delay matching for clock distribution in a logic circuit 有权
    逻辑电路中时钟分布的延迟匹配

    公开(公告)号：US07002390B2

    公开(公告)日：2006-02-21

    申请号：US11053167

    申请日：2005-02-07

    申请人： Octavian Florescu

    发明人： Octavian Florescu

    IPC分类号： H03K3/00

    CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K3/0372 ,  H03K3/0375 ,  H03K5/135

    摘要： Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

    摘要翻译： 用于补偿分布在逻辑电路内的信号之间的传播延迟差异的技术。 延迟匹配电路模拟翻转器产生的内部时钟到Q延迟。 延迟匹配电路被放置在要重新分配的诸如时钟信号的原始信号的传播路径中。 通常，延迟匹配电路可以包括具有特定配置的传播门复用器。 延迟匹配电路施加基本上等于由原始信号的分割版本经历的时钟到Q延迟的延迟。 以这种方式，延迟匹配电路确保原始信号和分频信号的上升沿和下降沿基本上对准，从而实现同步操作。 因此，延迟匹配电路能够使再分配和分割的信号同步。

    Model publishing framework
    7.
    发明申请
    Model publishing framework 有权
    模型出版框架

    公开(公告)号：US20070112793A1

    公开(公告)日：2007-05-17

    申请号：US11280538

    申请日：2005-11-14

    申请人： Octavian Florescu ,  Ian Leslie ,  Cheng-Yee Lin

    发明人： Octavian Florescu ,  Ian Leslie ,  Cheng-Yee Lin

    IPC分类号： G06F7/00

    CPC分类号： G06F17/211

    摘要： Provided are a method, system, and program for a model publishing framework. An intermediate data structure is generated from a model to include elements providing information on the model, wherein the model defines an object oriented program design. A publisher registry has a plurality of registered publishers. One registered publisher is selected from the publisher registry to use to publish the model. The publisher includes formatting information to generate model output. The selected publisher accesses the intermediate data structure and generates output from the elements in the intermediate data structure according to the formatting information to provide a visualization of the defined model.

    摘要翻译： 提供了一种用于模型发布框架的方法，系统和程序。 从模型生成中间数据结构以包括提供关于模型的信息的元素，其中模型定义面向对象的程序设计。 发布商注册表有多个已注册的发布商。 从发布商注册表中选择一个已注册的发布商用于发布模型。 发布商包括格式化信息以生成模型输出。 所选择的发布者访问中间数据结构，并根据格式化信息从中间数据结构中的元素生成输出，以提供定义模型的可视化。

    Delay matching for clock distribution in a logic circuit
    8.
    发明申请
    Delay matching for clock distribution in a logic circuit 有权
    逻辑电路中时钟分布的延迟匹配

    公开(公告)号：US20050134348A1

    公开(公告)日：2005-06-23

    申请号：US11053167

    申请日：2005-02-07

    申请人： Octavian Florescu

    发明人： Octavian Florescu

    IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K3/037 ,  H03K5/135 ,  H03L7/00

    CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K3/0372 ,  H03K3/0375 ,  H03K5/135

    摘要： Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

    摘要翻译： 用于补偿分布在逻辑电路内的信号之间的传播延迟差异的技术。 延迟匹配电路模拟翻转器产生的内部时钟到Q延迟。 延迟匹配电路被放置在要重新分配的诸如时钟信号的原始信号的传播路径中。 通常，延迟匹配电路可以包括具有特定配置的传播门复用器。 延迟匹配电路施加基本上等于由原始信号的分割版本经历的时钟到Q延迟的延迟。 以这种方式，延迟匹配电路确保原始信号和分频信号的上升沿和下降沿基本上对准，从而实现同步操作。 因此，延迟匹配电路能够使再分配和分割的信号同步。

    Delay matching for clock distribution in a logic circuit
    9.
    发明申请
    Delay matching for clock distribution in a logic circuit 有权

    公开(公告)号：US20050024116A1

    公开(公告)日：2005-02-03

    申请号：US10632651

    申请日：2003-07-31

    申请人： Octavian Florescu

    发明人： Octavian Florescu

    IPC分类号： G06F1/04 ,  G06F1/10 ,  H03K3/037 ,  H03K5/135 ,  H03K3/00

    CPC分类号： G06F1/04 ,  G06F1/10 ,  H03K3/0372 ,  H03K3/0375 ,  H03K5/135

    摘要： Techniques for compensating for propagation delay differences between signals distributed within a logic circuit. A delay matching circuit mimics the internal clock-to-Q delay produced by a flop. The delay matching circuit is placed in the propagation path of an original signal, such as a clock signal, to be redistributed. In general, the delay matching circuit may include a propagation gate multiplexer have a particular configuration. The delay matching circuit imposes a delay substantially equal to the clock-to-Q delay experienced by divided versions of the original signal. In this manner, the delay matching circuit ensures that the rising and falling edges of the original signal and the divided signal are in substantial alignment, enabling synchronous operation. Hence, the delay matching circuit is capable of synchronizing the redistributed and divided signals.

    Low-leakage current sources and active circuits
    10.
    发明申请
    Low-leakage current sources and active circuits 有权
    低漏电流源和有源电路

    公开(公告)号：US20060290416A1

    公开(公告)日：2006-12-28

    申请号：US11165269

    申请日：2005-06-22

    申请人： Octavian Florescu

    发明人： Octavian Florescu

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262 ,  G05F1/575

    摘要： A low-leakage circuit includes first, second, and third transistors, which may be P-channel or N-channel FETs. The first transistor provides an output current when enabled and presents low leakage current when disabled. The second transistor enables or disables the first transistor. The third transistor connects or isolates the first transistor to/from a predetermined voltage (e.g., VDD or VSS). The circuit may further include a pass transistor that provides a reference voltage to the source of the first transistor when the first transistor is disabled. In an ON state, the first transistor provides the output current, and the second and third transistors do not impact performance. In an OFF state, the second and third transistors are used to provide appropriate voltages to the first transistor to place it in a low-leakage state. The first, second, and third transistors may be used for a low-leakage current source within a current mirror, an amplifier stage, and so on.

    摘要翻译： 低泄漏电路包括第一，第二和第三晶体管，其可以是P沟道或N沟道FET。 第一个晶体管在使能时提供输出电流，并在禁用时呈现低泄漏电流。 第二晶体管启用或禁用第一晶体管。 第三晶体管将第一晶体管连接或隔离预定电压（例如，V DD或V SS SS）。 电路还可以包括传输晶体管，当第一晶体管被禁用时，该传输晶体管向第一晶体管的源极提供参考电压。 在导通状态下，第一晶体管提供输出电流，第二和第三晶体管不影响性能。 在OFF状态下，第二和第三晶体管用于向第一晶体管提供适当的电压以将其置于低泄漏状态。 第一，第二和第三晶体管可以用于电流镜，放大器级等内的低泄漏电流源。