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公开(公告)号：US12192000B2
公开(公告)日：2025-01-07
申请号：US18532791
申请日：2023-12-07
Inventor： Yutaka Murakami , Shutai Okamura , Kiyotaka Kobayashi , Masayuki Orihashi , Kazuaki Takahashi
Abstract: A transmitter apparatus wherein a simple structure is used to successfully suppress the degradation of error rate performance that otherwise would be caused by fading or the like. There are included encoding parts that encode transport data; a mapping part that performs such a mapping that encoded data sequentially formed by the encoding parts are not successively included in the same symbol, thereby forming data symbols; and a symbol interleaver that interleaves the data symbols. In this way, a low computational complexity can be used to perform an interleaving process equivalent to a bit interleaving process to effectively improve the reception quality at a receiving end.
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公开(公告)号：US12191945B2
公开(公告)日：2025-01-07
申请号：US18388965
申请日：2023-11-13
Inventor： Yutaka Murakami , Tomohiro Kimura , Mikihiro Ouchi , Hiroyuki Motozuka
IPC: H04B7/0456 , H04B7/0413 , H04B7/0417 , H04B7/06
Abstract: A transmission device includes: a weighting synthesizer that generates a first precoded signal and a second precoded signal; a first pilot inserter that inserts a pilot signal into the first precoded signal; a phase changer that applies a phase change of i×Δλ to the second precoded signal, where i is a symbol number and an integer that is greater than or equal to 0; an inserter that inserts a pilot signal into the phase-changed second precoded signal; and a phase changer that applies a phase change to the phase-changed and pilot-signal-inserted second precoded signal. Δλ satisfies π/2 radians
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公开(公告)号：US12184376B2
公开(公告)日：2024-12-31
申请号：US18349671
申请日：2023-07-10
Inventor： Yutaka Murakami , Tomohiro Kimura , Mikihiro Ouchi
IPC: H04B7/06 , H04B7/0452 , H04B7/0456 , H04L1/00 , H04L1/06 , H04B1/707 , H04L27/00 , H04L27/26
Abstract: A transmission apparatus includes M signal processors that respectively generate modulated signals directed to M reception apparatuses, M being an integer equal to or greater than 2, and an antenna section. Each signal processor modulates a first bit sequence made up of two bits to generate a first modulated signal and a second modulated signal, and modulates a second bit sequence made up of other two bits to generate a third modulated signal and a fourth modulated signal, in a case of transmitting multiple streams to a corresponding one of the M reception apparatuses. The antenna section includes a first antenna that transmits the first modulated signal and the third modulated signal and a second antenna that transmits the second modulated signal and the fourth modulated signal. At least either the signals transmitted from the first antenna or the signals transmitted from the second antenna are phase-changed signals.
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公开(公告)号：US12132540B2
公开(公告)日：2024-10-29
申请号：US18343620
申请日：2023-06-28
Inventor： Yutaka Murakami , Tomohiro Kimura , Mikihiro Ouchi
IPC: H04B7/04 , H04B7/0413 , H04B7/0452 , H04B7/0456 , H04B7/06
CPC classification number: H04B7/0456 , H04B7/0413 , H04B7/0452 , H04B7/0628 , H04B7/0671
Abstract: Provided are M signal processors that respectively generate modulated signals for M reception apparatuses (where M is an integer equal to 2 or greater), a multiplexing signal processor, and N antenna sections (where N is an integer equal to 1 or greater). When transmitting multiple streams, each of the M signal processors generates two mapped signals, generates first and second precoded signals by precoding the two mapped signals, periodically changes the phase of signal points in the IQ plane with respect to the second precoded signal, outputs the phase-changed signal, and outputs the first precoded signal and the phase-changed second precoded signal as two modulated signals. When transmitting a single stream, each of the M signal processor outputs a single modulated signal. The multiplexing signal processor multiplexes the modulated signals output from the M signal processors, and generates N multiplexed signals. The N antenna sections respectively transmit the N multiplexed signals.
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公开(公告)号：US12119900B2
公开(公告)日：2024-10-15
申请号：US18110543
申请日：2023-02-16
Inventor： Yutaka Murakami , Hiroyuki Motozuka
IPC: H04B7/0456 , H04B1/04 , H04L27/20
CPC classification number: H04B7/0456 , H04B1/0475 , H04L27/206
Abstract: A transmission device includes: a weighting synthesizer that generates a first precoded signal and a second precoded signal from a first baseband signal and a second baseband signal, respectively; a phase changer that applies a phase change of i×Δλ to the second precoded signal; an inserter that inserts a pilot signal into the second precoded signal applied with the phase change; and a phase changer that applies a phase change to the second precoded signal applied with the phase change and inserted with the pilot signal. The weighting synthesizer performs, in the precoding process, a calculation that uses
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21
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on the first baseband signal and the second baseband signal modulated via a modulation scheme of QPSK.-
Patent Agency Ranking
公开(公告)号：US11811479B2
公开(公告)日：2023-11-07
申请号：US18065533
申请日：2022-12-13
Inventor： Yutaka Murakami , Tomohiro Kimura , Mikihiro Ouchi
IPC: H04B7/06 , H04B7/0452 , H04L1/06 , H04L1/00 , H04B7/0456 , H04L27/26 , H04B1/707 , H04L27/00
CPC classification number: H04B7/0682 , H04B7/0452 , H04B7/0456 , H04B7/0697 , H04L1/0003 , H04L1/0618 , H04B1/707 , H04B7/0602 , H04B2201/70703 , H04L27/0008 , H04L27/2602 , H04L27/2626 , Y02D30/70
Abstract: A transmission apparatus includes M signal processors that respectively generate modulated signals directed to M reception apparatuses, M being an integer equal to or greater than 2, and an antenna section. Each signal processor modulates a first bit sequence made up of two bits to generate a first modulated signal and a second modulated signal, and modulates a second bit sequence made up of other two bits to generate a third modulated signal and a fourth modulated signal, in a case of transmitting multiple streams to a corresponding one of the M reception apparatuses. The antenna section includes a first antenna that transmits the first modulated signal and the third modulated signal and a second antenna that transmits the second modulated signal and the fourth modulated signal. At least either the signals transmitted from the first antenna or the signals transmitted from the second antenna are phase-changed signals.
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公开(公告)号：US11757569B2
公开(公告)日：2023-09-12
申请号：US17964180
申请日：2022-10-12
Inventor： Yutaka Murakami , Tomohiro Kimura , Mikihiro Ouchi
CPC classification number: H04L1/0068 , H03M13/1102 , H03M13/2906 , H03M13/616 , H03M13/6362 , H03M13/6516 , H04L1/0009 , H04L1/0041 , H04L1/0045 , H04L1/0057
Abstract: One coding method of a plurality of coding methods including at least a first coding method and a second coding method is selected, an information sequence is encoded by using the selected coding method, and an encoded sequence obtained by performing predetermined processing on the information sequence is modulated and transmitted. The first coding method is a coding method having a first coding rate, for generating a first encoded sequence by performing puncturing processing on a generated first codeword by using a first parity check matrix. The second coding method is a coding method having a second coding rate, for generating a second encoded sequence by performing puncturing processing on a generated second codeword by using a second parity check matrix that is different from the first parity check matrix, the second coding rate after the puncturing process being different from the first coding rate.
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公开(公告)号：US11742984B2
公开(公告)日：2023-08-29
申请号：US17344020
申请日：2021-06-10
Inventor： Yutaka Murakami , Shutai Okamura
IPC: H04L1/00 , H03M13/11 , H03M13/27 , H03M13/35 , H03M13/37 , H03M13/00 , H04L1/1812 , H04L1/1867 , H04L1/08 , H03M13/17
CPC classification number: H04L1/0041 , H03M13/1154 , H03M13/17 , H03M13/2703 , H03M13/2707 , H03M13/353 , H03M13/356 , H03M13/373 , H03M13/6306 , H03M13/6356 , H04L1/0045 , H04L1/0057 , H04L1/08 , H04L1/1819 , H04L1/1877 , H03M13/3761
Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q−1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q−1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q−1)≤n.
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公开(公告)号：US11722156B2
公开(公告)日：2023-08-08
申请号：US17459310
申请日：2021-08-27
Inventor： Yutaka Murakami
CPC classification number: H03M13/2792 , H03M13/1102 , H03M13/23 , H03M13/235 , H03M13/353 , H03M13/6502 , H03M13/6516 , H04L1/0041
Abstract: A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.
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公开(公告)号：US11653045B2
公开(公告)日：2023-05-16
申请号：US17727243
申请日：2022-04-22
Inventor： Yutaka Murakami , Tomohiro Kimura
IPC: H04N21/242 , H04H20/18 , H04N21/2381 , H04N21/462
CPC classification number: H04N21/242 , H04H20/18 , H04N21/2381 , H04N21/462 , H04N21/4622
Abstract: Provided is a method for transmitting a broadcasting content and a line content, the broadcasting content and the line content being synchronously displayed, the method including: generating a line parity packet from a plurality of line data packets in each of which the line content is stored; transmitting the line data packet and the line parity packet through a communication line; and transmitting a plurality of broadcasting data packets in each of which the broadcasting content is stored, from a base station using a broadcasting wave, a transfer clock time of the broadcasting content being delayed by a predetermined time compared with a transfer clock time of the line content. At this point, video quality can be improved when the real-time broadcasting program content and the real-time line content are simultaneously displayed.
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