公开(公告)号：US20200186145A1

公开(公告)日：2020-06-11

申请号：US16793970

申请日：2020-02-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shuichi NAGAI ,  Shingo ENOMOTO ,  Noboru NEGORO ,  Yasufumi KAWAI ,  Songbaek CHOE ,  Osamu TABATA

IPC: H03K17/567 ,  H02M7/217

Abstract: A gate driving circuit that controls a switching element includes: a startup switch which is provided between a gate voltage source and an output terminal; a termination switch which is provided between the output terminal and an output ground terminal; a startup resistor provided between a gate and a source of the startup switch; and a termination resistor provided between a gate and a source of the termination switch. At least one of the startup resistor or the termination resistor is configured to adjust a resistance value.

公开(公告)号：US20240048139A1

公开(公告)日：2024-02-08

申请号：US18264556

申请日：2021-10-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Koji TAKAHASHI ,  Manabu YANAGIHARA ,  Noboru NEGORO ,  Takeshi AZUMA

IPC: H03K17/30 ,  H03K17/0412 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K17/302 ,  H03K17/04123 ,  H03K19/0013 ,  H03K19/00361

Abstract: A gate drive circuit that drives a switching element including a first drain, a first source, and a first gate includes: a first terminal to which a gate control signal is input; a gate signal line connecting the first terminal and the first gate; a resistance element inserted in the gate signal line; a capacitance element connected in parallel with the resistance element; a clamp circuit that performs a clamp operation of clamping a voltage between the first gate and the first source to a voltage lower than a threshold voltage of the switching element when the gate control signal indicates an off period of the switching element; and a clamp control circuit that controls whether to prohibit the clamp operation of the clamp circuit in the off period.

公开(公告)号：US20220345128A1

公开(公告)日：2022-10-27

申请号：US17640980

申请日：2020-12-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yuta NAGATOMI ,  Shingo ENOMOTO ,  Songbaek CHOE ,  Osamu TABATA ,  Noboru NEGORO

IPC: H03K17/567 ,  H03K17/06 ,  H03K17/16 ,  H02M1/00

Abstract: A gate drive circuit that drives a power device by controlling charge and discharge of gate capacitance of the power device includes: a first semiconductor switch that charges the gate capacitance by being brought into conduction according to a first control signal; a second semiconductor switch that discharges the gate capacitance by being brought into conduction according to a second control signal; and a slew rate control circuit that is connected between a gate of the power device and a ground line, and controls a slew rate during discharge. The slew rate control circuit includes a capacitor and a third semiconductor switch connected in series. The third semiconductor switch is brought into conduction according to the second control signal.