公开(公告)号：US07519823B1

公开(公告)日：2009-04-14

申请号：US10917042

申请日：2004-08-12

申请人： Paul R. Schumacher ,  Robert D. Turney ,  Mark Paluszkiewicz ,  Prasanna Sundararajan ,  Brandon J. Blodget

发明人： Paul R. Schumacher ,  Robert D. Turney ,  Mark Paluszkiewicz ,  Prasanna Sundararajan ,  Brandon J. Blodget

IPC分类号： H04L9/00

CPC分类号： G06F21/76 ,  G06F21/16 ,  H04L9/0662 ,  H04L2209/12 ,  H04L2209/16 ,  H04L2209/608

摘要： Various approaches for embedding identifier information in a configuration bitstream for a programmable logic device (PLD) are disclosed. In various embodiments, the bits in the configuration bitstream that are unused in implementing a the design are identified. The identifier information is encrypted, and a subset of the unused bits are selected using a pseudo-random function. The encrypted identifier information is placed in the selected subset of unused bits. Decryption is accomplished by reversing the encryption approach.

摘要翻译： 公开了用于在可编程逻辑器件（PLD）的配置比特流中嵌入标识符信息的各种方法。 在各种实施例中，识别在实现设计时未使用的配置比特流中的比特。 标识符信息被加密，并且使用伪随机函数来选择未使用位的子集。 加密的标识符信息被放置在所选未使用的子集的子集中。 解密是通过逆转加密方法来实现的。

公开(公告)号：US07933277B1

公开(公告)日：2011-04-26

申请号：US11433126

申请日：2006-05-12

申请人： Paul R. Schumacher ,  Robert D. Turney

发明人： Paul R. Schumacher ,  Robert D. Turney

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04N19/42 ,  H04N19/30 ,  H04N19/61

摘要： Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.

摘要翻译： 描述了用于处理具有基础层和至少一个增强层的可缩放内容的方法和装置。 在一个示例中，提供了具有解码器逻辑和系统监视逻辑的静态逻辑。 还提供了具有多个可重构槽的可编程逻辑。 解码器逻辑包括用于处理可扩展内容的基本层的基本层处理器。 系统监视器逻辑被配置为利用至少一个增强块来动态地重新配置多个可重配置时隙中的至少一个，用于处理可扩展内容的至少一个增强层。

公开(公告)号：US07743176B1

公开(公告)日：2010-06-22

申请号：US11076798

申请日：2005-03-10

申请人： Robert D. Turney ,  Paul R. Schumacher

发明人： Robert D. Turney ,  Paul R. Schumacher

IPC分类号： G06F13/28 ,  G06F13/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/28

摘要： Method and apparatus for communication between hardware blocks configured in a programmable logic device (PLD) and a computation device external to the PLD is described. A bus controller is provided for receiving words from the computation device. Each of the words includes an address component and a data component. A first-in-first-out buffer (FIFO) is configured for communication with the bus controller to store the words. A processing engine is provided having a memory space associated with the hardware blocks and being configured to receive a word at a top of the FIFO. An address decoder is provided for decoding the address component of the word at the top of the FIFO to obtain an address of a memory location in the memory space. A strobe generator is provided for coupling a strobe signal to the processing engine. The strobe signal is configured to store the word in the memory location.

摘要翻译： 描述了在可编程逻辑器件（PLD）中配置的硬件块与PLD外部的计算设备之间进行通信的方法和装置。 提供总线控制器用于从计算装置接收单词。 每个单词包括地址组件和数据组件。 先进先出缓冲器（FIFO）被配置为与总线控制器通信以存储字。 提供了具有与硬件块相关联的存储器空间并且被配置为在FIFO的顶部接收单词的处理引擎。 提供地址解码器用于对在FIFO顶部的单词的地址分量进行解码以获得存储器空间中的存储器位置的地址。 提供选通发生器用于将选通信号耦合到处理引擎。 选通信号被配置为将字存储在存储器位置中。

公开(公告)号：US07359276B1

公开(公告)日：2008-04-15

申请号：US11235924

申请日：2005-09-27

申请人： Robert D. Turney ,  Paul R. Schumacher ,  Kornelis Antonius Vissers

发明人： Robert D. Turney ,  Paul R. Schumacher ,  Kornelis Antonius Vissers

IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/4059 ,  G06F5/14

摘要： An aspect of the invention relates to communication between a first processing element and a second processing element. A first-in-first-out circuit (FIFO) includes a data input port, a data output port, an object-sent port, an object-end port, a memory, and control logic. The data input port is coupled to the first processing element. The data output port is coupled to the second processing element. The object-sent port is configured to receive an object-sent signal from the first processing element. The object-end port is configured to send an object-end signal to the second processing element. The memory is configured to store objects, each of the objects include a plurality of data words. The control logic is configured to control reading and writing to the memory, processing the object sent signal, and generating the object end signal.

摘要翻译： 本发明的一个方面涉及第一处理元件和第二处理元件之间的通信。 先进先出电路（FIFO）包括数据输入端口，数据输出端口，对象发送端口，对象端口，存储器和控制逻辑。 数据输入端口耦合到第一处理元件。 数据输出端口耦合到第二处理元件。 对象发送端口被配置为从第一处理元件接收对象发送的信号。 对象端口被配置为向第二处理元件发送目标端信号。 存储器被配置为存储对象，每个对象包括多个数据字。 控制逻辑被配置为控制对存储器的读取和写入，处理对象发送的信号以及生成对象结束信号。

公开(公告)号：US07684278B1

公开(公告)日：2010-03-23

申请号：US12198733

申请日：2008-08-26

申请人： Paul R. Schumacher ,  Mark Paluszkiewicz ,  Kornelis A. Vissers

发明人： Paul R. Schumacher ,  Mark Paluszkiewicz ,  Kornelis A. Vissers

IPC分类号： G11C8/00

CPC分类号： G06F5/16

摘要： Method and apparatus for implementing first-in-first-out (FIFO) memories using time-multiplexed memory in an integrated circuit are described. A block random access memory (BRAM) circuit embedded in the integrated circuit is provided. The BRAM includes at least one port responsive to a respective at least one BRAM clock signal. FIFO logic is configured to implement a plurality of FIFOs in the BRAM having a plurality of interfaces. Multiplexer logic is configured to selectively couple the plurality of output interfaces of the FIFO logic to the at least one port of the BRAM circuit responsive to at least one FIFO clock signal. Each of the at least one BRAM clock signal has at least twice the frequency of a respective one of the at least one FIFO clock signal.

摘要翻译： 描述了使用集成电路中的时分复用存储器来实现先进先出（FIFO）存储器的方法和装置。 提供嵌入在集成电路中的块随机存取存储器（BRAM）电路。 BRAM包括响应于相应的至少一个BRAM时钟信号的至少一个端口。 FIFO逻辑被配置为在具有多个接口的BRAM中实现多个FIFO。 多路复用器逻辑被配置为响应于至少一个FIFO时钟信号，将FIFO逻辑的多个输出接口选择性地耦合到BRAM电路的至少一个端口。 所述至少一个BRAM时钟信号中的每一个具有至少一个FIFO时钟信号中相应一个的频率的至少两倍。

公开(公告)号：US20130320015A1

公开(公告)日：2013-12-05

申请号：US13910806

申请日：2013-06-05

申请人： Richard J. Dyble ,  Paul R. Schumacher ,  Timothy M. Stirmel

发明人： Richard J. Dyble ,  Paul R. Schumacher ,  Timothy M. Stirmel

IPC分类号： B65D43/02

CPC分类号： B65D43/0266 ,  B65D43/0249 ,  B65D2543/00194 ,  B65D2543/00296 ,  B65D2543/00555 ,  B65D2543/0062 ,  B65D2543/00685 ,  B65D2543/00731 ,  B65D2543/00796 ,  B65D2543/00842

摘要： Disclosed is a tamper evident packaging that provides a packaging piece with a lid, a base section, and tamper evidencing means. The tamper evidencing means is provided on the base of the packaging piece by way of an internal and external rib structure with a perforated channel formed therebetween. The lid is configured with an engagement portion having a lid flange that is positioned within the perforated channel when the packaging is closed, thereby prohibiting access to the lid flange and preventing the opening of and tampering with the packaging piece. The perforated channel allows for the removal of the external rib structure from the interior rib structure, thereby granting access to the lid flange and allowing for the packaging to be opened, as well as providing the evidence that the packaging may have been tampered with.

摘要翻译： 公开了一种防拆封包装，其提供具有盖子，基座部分和篡改证明装置的包装件。 篡改证明装置通过内部和外部肋结构设置在包装件的基部上，其间形成有穿孔通道。 盖子配置有接合部分，该接合部分具有盖子凸缘，当盖子封闭时，该凸缘定位在穿孔通道内，从而禁止进入盖子凸缘并防止打开和篡改包装件。 穿孔通道允许从内部肋结构移除外部肋结构，从而允许进入盖凸缘并允许打开包装，以及提供包装可能被篡改的证据。

公开(公告)号：US08473272B1

公开(公告)日：2013-06-25

申请号：US12684527

申请日：2010-01-08

申请人： Adam P. Donlin ,  Paul R. Schumacher

发明人： Adam P. Donlin ,  Paul R. Schumacher

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/02

摘要： Approaches for preparing a system that is reconfigurable to implement a plurality of optional hardware functions are disclosed. In one approach, a method includes simulating the operation of the system during a time interval. The system is reconfigurable to implement a subset of the optional hardware functions, and the simulating determines which of the optional hardware functions are active and which of the optional hardware functions are inactive during a plurality of subintervals of the time interval. Respective circuit resource sets are estimated for the subintervals of the time interval. For each of the subintervals, the respective circuit resource set implements the system including the optional hardware functions that are active during the subinterval. Information describing the respective circuit resource sets for the subintervals is stored for preparing partial reconfigurations of the system.

摘要翻译： 公开了用于准备可重构以实现多个可选硬件功能的系统的方法。 在一种方法中，一种方法包括在时间间隔期间模拟系统的操作。 该系统是可重构的以实现可选硬件功能的子集，并且模拟确定在时间间隔的多个子间隔期间哪个可选硬件功能是活动的以及哪个可选硬件功能是无效的。 对于时间间隔的子区间估计相应的电路资源集合。 对于每个子间隔，相应的电路资源集实现包括在子间隔期间有效的可选硬件功能的系统。 存储描述用于子区间的相应电路资源集的信息，用于准备系统的部分重新配置。

公开(公告)号：US09117046B1

公开(公告)日：2015-08-25

申请号：US12041167

申请日：2008-03-03

申请人： Paul R. Schumacher ,  Ian D. Miller ,  David B. Parlour ,  Jorn W. Janneck ,  Pradip Kumar Jha

发明人： Paul R. Schumacher ,  Ian D. Miller ,  David B. Parlour ,  Jorn W. Janneck ,  Pradip Kumar Jha

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F2217/72

摘要： A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.

摘要翻译： 公开了一种生成用于估计电路设计的资源需求的数据的方法。 该方法包括识别用于电路设计的网表的多个中间电路模块; 根据相关联的多个参数集详细描述多个中间电路模块的每个中间电路模块; 生成每个中间电路模块的资源估计和相关联的多个参数集的参数集合; 并存储用于中间电路模块的资源估计。

公开(公告)号：US08407653B1

公开(公告)日：2013-03-26

申请号：US13217496

申请日：2011-08-25

申请人： Paul R. Schumacher ,  Austin H. Lesea

发明人： Paul R. Schumacher ,  Austin H. Lesea

IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22 ,  H03K19/007 ,  H03K19/003 ,  H03K17/16

CPC分类号： G06F11/008 ,  G06F17/5022 ,  G06F2217/14

摘要： Approaches for estimating a derating factor for a plurality of potential soft errors in a circuit implementation of a circuit design. A plurality of respective estimated toggle rates are determined for a plurality of circuit elements for implementing the circuit design. A derating factor of the circuit design is determined as a function of the estimated toggle rates of the plurality of circuit elements. The derating factor is an estimation of a fraction of the plurality of potential soft errors that would cause functional failure of the circuit design.

摘要翻译： 用于估计电路设计的电路实现中的多个潜在软错误的降额因子的方法。 为了实现电路设计，为多个电路元件确定多个相应的估计拨动率。 电路设计的降额因子被确定为多个电路元件的估计切换速率的函数。 降额因子是对导致电路设计的功能失效的多个潜在软错误的一部分的估计。

公开(公告)号：US08146035B1

公开(公告)日：2012-03-27

申请号：US12398270

申请日：2009-03-05

申请人： Paul R. Schumacher ,  Smitha Sundaresan ,  Alan Frost ,  Pradip K. Jha

发明人： Paul R. Schumacher ,  Smitha Sundaresan ,  Alan Frost ,  Pradip K. Jha

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/504 ,  G06F2217/78

摘要： Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a plurality of circuit elements for implementing the circuit design. The circuit elements are matched to structural templates. Each structural template is representative of one or more circuit elements and has associated information descriptive of one or more toggle rates. Respective estimated toggle rates are determined for the circuit elements of the circuit design based on the information descriptive of one or more toggle rates associated with the matched structural templates. An estimated power consumption level is determined as a function of the estimated toggle rates of the circuit elements, and data indicative of the estimated power consumption level is output.

摘要翻译： 从电路设计估计电路功耗的方法。 根据一个实施例，电路设计的表示指定用于实现电路设计的多个电路元件。 电路元件与结构模板相匹配。 每个结构模板代表一个或多个电路元件，并具有描述一个或多个切换率的相关信息。 基于描述与匹配的结构模板相关联的一个或多个切换速率的信息来确定电路设计的电路元件的相应估计的切换率。 作为电路元件的估计切换速率的函数来确定估计的功率消耗水平，并且输出表示估计的功耗水平的数据。