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    Inverter circuit having a feedback switch and methods corresponding thereto
    1.
    发明授权
    Inverter circuit having a feedback switch and methods corresponding thereto 失效
    具有反馈开关的逆变器电路及其对应的方法

    公开(公告)号：US07550998B2

    公开(公告)日：2009-06-23

    申请号：US11259480

    申请日：2005-10-26

    申请人： Paul W. Brazis ,  Daniel R. Gamota ,  Kin P. Tsui ,  John B. Szczech ,  Jie Zhang

    发明人： Paul W. Brazis ,  Daniel R. Gamota ,  Kin P. Tsui ,  John B. Szczech ,  Jie Zhang

    IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03K19/20

    CPC分类号： H03K19/01721 ,  H03K19/09441

    摘要： An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched “off,” to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.

    摘要翻译： 一种具有可操作地耦合到电压偏置输入（101）的驱动晶体管（102）的逆变器电路（500），并且其中该驱动晶体管通过打开和关闭输出（105）和地（ 104））进一步可操作地耦合到反馈开关（401）。 在优选的方法中，反馈开关本身也可操作地耦合到电压偏置输入端和输出端，并且优选地在驱动晶体管被切断时关断，以将电压偏置输入以驱动晶体管的方式耦合到驱动晶体管， 以使驱动晶体管的栅极端子相对于驱动晶体管的源极端子的极性相反，从而允许逆变器电路在驱动晶体管的基本上全部的电位工作范围内工作。

    Semiconductor device and method for providing a reduced surface area electrode
    3.
    发明授权
    Semiconductor device and method for providing a reduced surface area electrode 失效
    用于提供减小的表面积电极的半导体器件和方法

    公开(公告)号：US07355225B2

    公开(公告)日：2008-04-08

    申请号：US11258634

    申请日：2005-10-26

    申请人： Paul W. Brazis ,  Daniel R. Gamota ,  Krishna Kalyanasundaram ,  Jie Zhang

    发明人： Paul W. Brazis ,  Daniel R. Gamota ,  Krishna Kalyanasundaram ,  Jie Zhang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/41733 ,  H01L27/1292 ,  H01L51/0022 ,  H01L51/055 ,  H01L51/102 ,  H01L2924/19043 ,  H01L2924/30105

    摘要： An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach the first electrode has a surface area that is reduced notwithstanding the aforementioned established perimeter. This, in turn, aids in reducing any corresponding parasitic capacitance. This reduction in surface area may be accomplished, for example, by providing openings (203) through certain portions of the first electrode.

    摘要翻译： 诸如半导体器件的装置（200）包括栅电极（201）和至少第一电极（202）。 第一电极优选地具有与栅电极至少部分重叠的确定的周边，从而形成对应的晶体管沟道。 在优选的方法中，尽管具有上述建立的周长，第一电极具有减小的表面积。 这又有助于减少任何相应的寄生电容。 表面积的这种减小可以例如通过提供通过第一电极的某些部分的开口（203）来实现。

    Method and Apparatus to Facilitate Testing of Printed Semiconductor Devices
    4.
    发明申请
    Method and Apparatus to Facilitate Testing of Printed Semiconductor Devices 审中-公开
    促进印刷半导体器件测试的方法和装置

    公开(公告)号：US20090098668A1

    公开(公告)日：2009-04-16

    申请号：US12270544

    申请日：2008-11-13

    申请人： Paul W. Brazis ,  Daniel R. Gamota ,  Krishna Kalyanasundaram ,  Jie Zhang ,  Krishna D. Jonnalagadda

    发明人： Paul W. Brazis ,  Daniel R. Gamota ,  Krishna Kalyanasundaram ,  Jie Zhang ,  Krishna D. Jonnalagadda

    IPC分类号： H01L21/66 ,  H01L21/302

    CPC分类号： H01L22/14 ,  H01L51/0005

    摘要： A printing platform receives (102) (preferably in-line with a semiconductor device printing process (101)) a substrate having at least one semiconductor device printed thereon and further having a test structure printed thereon, which test structure comprises at least one printed semiconductor layer. These teachings then provide for the automatic testing (103) of the test structure with respect to at least one static (i.e., relatively unchanging) electrical characteristic metric. The static electrical characteristic metric (or metrics) of choice will likely vary with the application setting but can include, for example, a measure of electrical resistance, a measure of electrical reactance, and/or a measure of electrical continuity. Optionally (though preferably) the semiconductor device printing process itself is then adjusted (105) as a function, at least in part, of this metric.

    摘要翻译： 印刷平台接收（优选地与半导体器件印刷工艺（101）成直角））具有印刷在其上的至少一个半导体器件并且还具有印刷在其上的测试结构的衬底，该测试结构包括至少一个印刷半导体 层。 然后，这些教导提供了关于至少一个静态（即，相对不变的）电特性度量的测试结构的自动测试（103）。 选择的静态电特性度量（或度量）可能随着应用设置而变化，但是可以包括例如电阻的测量，电抗的测量和/或电连续性的测量。 可选地（尽管优选地），然后至少部分地基于该度量来调整（105）半导体器件打印过程本身。

    Nanoparticle Semiconductor Device and Method for Fabricating
    5.
    发明申请
    Nanoparticle Semiconductor Device and Method for Fabricating 审中-公开
    纳米粒子半导体器件及其制造方法

    公开(公告)号：US20090057662A1

    公开(公告)日：2009-03-05

    申请号：US11846805

    申请日：2007-08-29

    申请人： Paul W. Brazis ,  Daniel R. Gamota ,  Dale R. McClure ,  Andrew F. Skipor ,  Jie Zhang

    发明人： Paul W. Brazis ,  Daniel R. Gamota ,  Dale R. McClure ,  Andrew F. Skipor ,  Jie Zhang

    IPC分类号： H01L29/12 ,  H01L21/20

    CPC分类号： H01L21/02601 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02628

    摘要： A low-temperature process for creating a semiconductive device by printing a liquid composition containing semiconducting nanoparticles. The semiconductive device is formed on a polymeric substrate by printing a composition that contains nanoparticles of inorganic semiconductor suspended in a carrier, using a graphic arts printing method. The printed deposit is then heated to remove substantially all of the carrier from the printed deposit. The low-temperature process does not heat the substrate or the printed deposit above 300° C. The mobility of the resulting semiconductive device is between about 10 cm2/Vs and 200 cm2/Vs.

    摘要翻译： 通过印刷含有半导体纳米颗粒的液体组合物来产生半导体器件的低温方法。 使用印刷技术印刷方法，通过印刷含有悬浮在载体中的无机半导体纳米颗粒的组合物，在聚合物基材上形成半导体装置。 然后加热印刷的沉积物以从印刷的沉积物中基本上除去所有的载体。 低温工艺不会将衬底或印刷沉积物加热到300℃以上。所得半导体器件的迁移率在约10cm 2 / Vs至200cm 2 / Vs之间。

    Organic semiconductor inverting circuit
    6.
    发明授权
    Organic semiconductor inverting circuit 失效
    有机半导体反相电路

    公开(公告)号：US07030666B2

    公开(公告)日：2006-04-18

    申请号：US10788627

    申请日：2004-02-27

    申请人： Paul W. Brazis ,  Hakeem B. Adewole ,  Daniel R. Gamota ,  Jie Zhang

    发明人： Paul W. Brazis ,  Hakeem B. Adewole ,  Daniel R. Gamota ,  Jie Zhang

    IPC分类号： H03B1/00 ,  H03K3/00

    CPC分类号： H03K19/08

    摘要： An organic semiconductor inverting circuit includes at least three organic transistors, an output terminal (110, 210, 310, 410), a reference supply voltage input (115, 215, 315, 415), a first positive supply voltage input (120, 220, 320, 420), and a negative supply voltage input (125, 225, 325, 425). One of the three organic transistors is an input transistor having a gate to which is coupled an input terminal (105, 205, 305, 405). The output terminal (110, 210, 310, 410) is coupled to a first electrode of at least one of the at least three organic transistors.

    摘要翻译： 有机半导体反相电路包括至少三个有机晶体管，输出端（110,210,310,410），参考电源电压输入（115,215,315,415），第一正电源电压输入端（120,220） ，320,420）和负电源电压输入（125,225,325,425）。 三个有机晶体管中的一个是具有与输入端（105,205,305,405）耦合的栅极的输入晶体管。 输出端子（110,210,310,410）耦合到至少三个有机晶体管中的至少一个的第一电极。

    Method of fabricating organic field effect transistors
    7.
    发明授权
    Method of fabricating organic field effect transistors 失效
    制造有机场效应晶体管的方法

    公开(公告)号：US07399656B2

    公开(公告)日：2008-07-15

    申请号：US11102166

    申请日：2005-04-08

    申请人： Jie Zhang ,  Paul W. Brazis ,  Daniel R. Gamota ,  Krishna Kalyanasundaram ,  Min-Xian M. Zhang

    发明人： Jie Zhang ,  Paul W. Brazis ,  Daniel R. Gamota ,  Krishna Kalyanasundaram ,  Min-Xian M. Zhang

    IPC分类号： H01L21/00

    CPC分类号： H01L51/0516 ,  H01L51/0024 ,  H01L51/0036 ,  H01L51/0051 ,  H01L51/0078 ,  H01L51/0084

    摘要： Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.

    摘要翻译： 有机场效应晶体管（OFET）可以通过使用在介质芯的每一侧上具有导电层（204,206）的多层膜（202）在有机膜上快速且低成本地产生。 图案化导电层以形成栅电极（214），并且使用热和压力（225）或粘合剂层（228）将聚合物膜（223）附着到多层电介质膜的栅电极侧。 然后在多层电介质膜的剩余侧上形成源电极和漏电极（236），并且在源电极和漏电极上沉积有机半导体（247），以填充源极和漏极之间的间隙 电极并且接触电介质膜的一部分以产生有机场效应晶体管。

    Electronic module interconnection apparatus
    9.
    发明授权
    Electronic module interconnection apparatus 失效
    电子模块互连设备

    公开(公告)号：US07492604B2

    公开(公告)日：2009-02-17

    申请号：US11379751

    申请日：2006-04-21

    申请人： Paul W. Brazis ,  Marc K. Chason ,  Daniel R. Gamota ,  Krishna Kalyanasundaram

    发明人： Paul W. Brazis ,  Marc K. Chason ,  Daniel R. Gamota ,  Krishna Kalyanasundaram

    IPC分类号： H05K1/11

    CPC分类号： H05K1/147 ,  H05K1/118 ,  H05K1/144 ,  H05K3/361 ,  H05K3/363 ,  H05K2201/041 ,  H05K2201/10189 ,  H05K2201/10674 ,  H05K2203/1572

    摘要： An electronic apparatus, includes a plurality of electronic modules, each having a maximum thickness of no more than 90 microns, each comprising a substrate having a two sided edge connection pattern. The electronic modules are arranged adjacent to each other. Each pad of a first set of connection pads on a first electronic module is conductively connected to an opposing pad of a second set of connection pads of a second electronic module. The first set of connection pads is separated from the second set of connection pads by electrically conductive material that is less than 15 microns thick.

    摘要翻译： 一种电子设备，包括多个电子模块，每个电子模块的最大厚度不超过90微米，每个电子模块包括具有双面边缘连接图案的基板。 电子模块彼此相邻布置。 第一电子模块上的第一组连接焊盘的每个焊盘导电地连接到第二电子模块的第二组连接焊盘的相对焊盘。 第一组连接焊盘通过小于15微米厚的导电材料与第二组连接焊盘分开。