公开(公告)号：US20180225066A1

公开(公告)日：2018-08-09

申请号：US15944041

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Michael Hawjing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F3/06 ,  G06F1/32 ,  G06F12/08

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US09312326B2

公开(公告)日：2016-04-12

申请号：US14688807

申请日：2015-04-16

Applicant: QUALCOMM, Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01G4/33 ,  H01G4/38 ,  H01G4/002 ,  H01G4/005

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第 第一和第二电极。 电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。 第一电极耦合到第一电源轨道，第三电极耦合到第二电源轨道，并且第二电源轨道具有比第一电源轨道更高的电源电压。

公开(公告)号：US20170228196A1

公开(公告)日：2017-08-10

申请号：US15016806

申请日：2016-02-05

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Reginin ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffery Gemar ,  Haw-Jing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US09965220B2

公开(公告)日：2018-05-08

申请号：US15016806

申请日：2016-02-05

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Haw-Jing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US20150294970A1

公开(公告)日：2015-10-15

申请号：US14252588

申请日：2014-04-14

Applicant: QUALCOMM Incorporated

Inventor： Renatas Jakushokas ,  Robert Won Chol Kim ,  Vaishnav Srinivas

IPC: H01L27/10 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L28/20 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor, resistor and resistor-capacitor components are described herein. In one embodiment, a die comprises first and second metal interconnect layers in a back end of line (BEOL) of the die, and an insulator between the first and second metal interconnect layers. The die also comprises a metal-insulator-metal (MIM) capacitor embedded in the insulator, the MIM capacitor comprising a first metal plate, a second metal plate, and a dielectric layer between the first and second metal plates. The die further comprises a metal resistor embedded in the insulator, wherein the metal resistor and the first metal plate of the MIM capacitor are formed from a same metal layer. In one example, the dielectric layer may have a higher dielectric constant than the insulator. In another example, the second metal plate of the MIM capacitor may overlap the metal resistor.

Abstract translation: 本文描述了电容器，电阻器和电阻器 - 电容器部件。 在一个实施例中，管芯包括管芯的后端（BEOL）中的第一和第二金属互连层以及第一和第二金属互连层之间的绝缘体。 模具还包括嵌入在绝缘体中的金属 - 绝缘体 - 金属（MIM）电容器，MIM电容器包括第一金属板，第二金属板和介于第一和第二金属板之间的电介质层。 模具还包括嵌入绝缘体中的金属电阻器，其中金属电阻器和MIM电容器的第一金属板由相同的金属层形成。 在一个示例中，电介质层可以具有比绝缘体更高的介电常数。 在另一示例中，MIM电容器的第二金属板可以与金属电阻器重叠。

公开(公告)号：US20140367757A1

公开(公告)日：2014-12-18

申请号：US13917549

申请日：2013-06-13

Applicant: QUALCOMM Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括低压电容器和高压电容器。 低电压电容器包括由第一金属层形成的第一电极，由第二金属层形成的第二电极，由第三金属层形成的第三电极，第一和第二电极之间的第一介电层，以及第二电极 电介质层在第二和第三电极之间。 高压电容器包括由第一金属层形成的第四电极，由第三金属层形成的第五电极和在第四和第五电极之间的第三电介质层，其中第三电介质层比第一电介质层厚 层或第二电介质层。

公开(公告)号：US10761774B2

公开(公告)日：2020-09-01

申请号：US15944041

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Michael Hawjing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F1/32 ,  G06F12/08 ,  G06F3/06 ,  G06F1/3234

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US20150221716A1

公开(公告)日：2015-08-06

申请号：US14688807

申请日：2015-04-16

Applicant: QUALCOMM, Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括由第一金属层形成的第一电极，由第二金属层形成的第二电极和由第三金属层形成的第三电极，其中第二和第三电极间隔比第 第一和第二电极。 电容器结构还包括在第一和第二电极之间的第一电介质层和在第二和第三金属层之间的第二电介质层，其中第二电介质层具有比第一电介质层更大的厚度。 第一电极耦合到第一电源轨，第三电极耦合到第二电源轨，并且第二电源轨具有比第一电源轨更高的电源电压。

公开(公告)号：US09041148B2

公开(公告)日：2015-05-26

申请号：US13917549

申请日：2013-06-13

Applicant: QUALCOMM Incorporated

Inventor： Renatas Jakushokas ,  Vaishnav Srinivas ,  Robert Won Chol Kim

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01G4/33 ,  H01G4/38 ,  H01G4/002

CPC classification number: H01L28/60 ,  H01G4/002 ,  H01G4/005 ,  H01G4/33 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract translation: 本文描述了能够提供低电压电容器和高压电容器的电容器结构。 在一个实施例中，电容器结构包括低压电容器和高压电容器。 低电压电容器包括由第一金属层形成的第一电极，由第二金属层形成的第二电极，由第三金属层形成的第三电极，第一和第二电极之间的第一介电层，以及第二电极 电介质层在第二和第三电极之间。 高压电容器包括由第一金属层形成的第四电极，由第三金属层形成的第五电极和在第四和第五电极之间的第三电介质层，其中第三电介质层比第一电介质层厚 层或第二电介质层。