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公开(公告)号：US09088285B2
公开(公告)日：2015-07-21
申请号：US13926923
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Jeremy Mark Goldblatt , Devavrata Vasant Godbole , Hsuanyu Pan
CPC classification number: H03K21/17 , H03K5/15033 , H03K23/425
Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.
Abstract translation: 高速和低功率分配器包括四个动态锁存器环，互锁电路和四个输出反相器。 每个锁存器具有第一动态节点M和第二动态节点N.互锁电路耦合到M个节点。 基于接收到的一个或多个M个节点信号，互锁电路选择性地控制M个模式中的一个或多个的逻辑值，使得随着时间的推移，当分频器被计时时，N个节点上的信号中只有一个为低 在给定的时间。 输出反相器产生从分频器输出的N个节点信号的反相版本，作为低相位噪声25％占空比输出信号I，IB，Q和QB。 在一个具体示例中，每个锁存器具有八个晶体管，不超过八个晶体管。 分离器快速自动地从错误的状态干扰中恢复。
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2.发明授权公开(公告)号：US09344270B2
公开(公告)日：2016-05-17
申请号：US13829232
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Li Liu , Praveen-Kumar Sampath , Lai Kan Leung , Chiewcharn Narathong , Soon-Seng Lau , Ketan Humnabadkar , Raghu Narayan Challa , Devavrata Vasant Godbole
CPC classification number: H04L7/0331 , H03B21/01 , H03D3/009 , H04W52/02 , H04W52/0209 , Y02D70/1222 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/164
Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.
Abstract translation: 公开了用于检测和校正本地振荡器（LO）信号的相位不连续性的技术。 在一种设计中，无线设备包括LO发生器和相位检测器。 LO发生器产生用于频率转换的LO信号，并且周期性地通电和关断。 当LO发生器通电时，相位检测器检测LO信号的相位。 LO信号的检测相位用于识别LO信号的相位不连续性。 无线设备还可以包括（i）生成用于检测LO信号的相位的单音信号的单音发生器，（ii）下变频器，其使用LO信号对单音信号进行下变频，并提供 相位检测器用于检测LO信号的相位的下变频信号，以及（iii）校正模拟域或数字域中的LO信号的相位不连续性的相位校正器。
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公开(公告)号：US20140376683A1
公开(公告)日：2014-12-25
申请号：US13926923
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Jeremy Mark Goldblatt , Devavrata Vasant Godbole , Hsuanyu Pan
IPC: H03K21/17
CPC classification number: H03K21/17 , H03K5/15033 , H03K23/425
Abstract: A high-speed and low power divider includes a ring of four dynamic latches, an interlocking circuit, and four output inverters. Each latch has a first dynamic node M and a second dynamic node N. The interlocking circuit is coupled to the M nodes. Based on one or more of the M node signals received, the interlocking circuit selectively controls the logic values on one or more of the M modes such that over time, as the divider is clocked, only one of the signals on the N nodes is low at a given time. The output inverters generate inverted versions of the N node signals that are output from the divider as low phase noise 25% duty cycle output signals I, IB, Q and QB. In one specific example, each latch has eight transistors and no more than eight transistors. The divider recovers quickly and automatically from erroneous state disturbances.
Abstract translation: 高速和低功率分配器包括四个动态锁存器环，互锁电路和四个输出反相器。 每个锁存器具有第一动态节点M和第二动态节点N.互锁电路耦合到M个节点。 基于接收到的一个或多个M个节点信号，互锁电路选择性地控制M个模式中的一个或多个的逻辑值，使得随着时间的推移，当分频器被计时时，N个节点上的信号中只有一个为低 在给定的时间。 输出反相器产生从分频器输出的N个节点信号的反相版本，作为低相位噪声25％占空比输出信号I，IB，Q和QB。 在一个具体示例中，每个锁存器具有八个晶体管，不超过八个晶体管。 分离器快速自动地从错误的状态干扰中恢复。
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4.发明申请公开(公告)号：US20140270032A1
公开(公告)日：2014-09-18
申请号：US13829232
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Li Liu , Praveen-Kumar Sampath , Lai Kan Leung , Chiewcharn Narathong , Soon-Seng Lau , Ketan Humnabadkar , Raghu Narayan Challa , Devavrata Vasant Godbole
CPC classification number: H04L7/0331 , H03B21/01 , H03D3/009 , H04W52/02 , H04W52/0209 , Y02D70/1222 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/164
Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. In one design, a wireless device includes an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may further include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.
Abstract translation: 公开了用于检测和校正本地振荡器（LO）信号的相位不连续性的技术。 在一种设计中，无线设备包括LO发生器和相位检测器。 LO发生器产生用于频率转换的LO信号，并且周期性地通电和关断。 当LO发生器通电时，相位检测器检测LO信号的相位。 LO信号的检测相位用于识别LO信号的相位不连续性。 无线设备还可以包括（i）生成用于检测LO信号的相位的单音信号的单音发生器，（ii）下变频器，其使用LO信号对单音信号进行下变频，并提供 相位检测器用于检测LO信号的相位的下变频信号，以及（iii）校正模拟域或数字域中的LO信号的相位不连续性的相位校正器。
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