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公开(公告)号：US12267090B2
公开(公告)日：2025-04-01
申请号：US17934784
申请日：2022-09-23
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Yunfei Feng , Vinod Panikkath , Li Liu , Sher Jiun Fang
Abstract: Aspects of the disclosure relate to wireless communication apparatuses, methods, and other aspects of sliding intermediate frequency filters for carrier aggregation communications. One aspect a high band mixer including a radio frequency (RF) receive signal input, a local oscillator (LO) input, and an IF signal output, a tunable high pass filter including an input and an output, an intermediate frequency (IF) received signal multiplexer including a merged IF CA signal output, a first input, and a second input, an LO input, and an IF signal output, where the RF receive signal input is coupled to the low band mmW CA receive port, and a tunable low pass filter including an input and an output, where the input is coupled to the IF signal output of the low band mixer, and where the output is coupled to the second input of the IF received signal multiplexer.
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公开(公告)号：US20240178795A1
公开(公告)日：2024-05-30
申请号：US18060295
申请日：2022-11-30
Applicant: Qualcomm Incorporated
Inventor： Mohamed Abouzied , Chuan Wang , Anosh Davierwalla , Muhammad Hassan , Vinod Panikkath , Li Liu
CPC classification number: H03D7/1491 , H04B17/21
Abstract: An apparatus is disclosed for oscillator feedthrough calibration, such as a component arrangement that can be calibrated to account for signal leakage from an oscillator coupled to a mixer circuit. In example aspects, the apparatus includes a mixer circuit having a first stage, a second stage, and tuning circuitry. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The one or more transistors are also coupled between a local oscillator signal input and the mixer output. The tuning circuitry includes at least one current source coupled to the at least one transistor of the first stage.
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公开(公告)号：US11862861B2
公开(公告)日：2024-01-02
申请号：US17653449
申请日：2022-03-03
Applicant: Qualcomm Incorporated
Inventor： Li Liu , Kevin Hsi Huai Wang , Yunfei Feng , Chuan Wang , Gurkanwal Sahota
CPC classification number: H01Q21/30 , H01Q5/35 , H04B1/18 , H04B1/44 , H01Q21/065
Abstract: An apparatus is disclosed for a hybrid wireless transceiver architecture that supports multiple antenna arrays. In an example aspect, the apparatus includes a first antenna array, a second antenna array, and a wireless transceiver. The wireless transceiver includes first dedicated circuitry dedicated to the first antenna array and second dedicated circuitry dedicated to the second antenna array. The wireless transceiver also includes shared circuitry that is shared with both the first antenna array and the second antenna array.
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公开(公告)号：US11750253B2
公开(公告)日：2023-09-05
申请号：US17464404
申请日：2021-09-01
Applicant: QUALCOMM Incorporated
Inventor： Chuan Wang , Bhushan Shanti Asuri , Li Liu , Vinod Panikkath
CPC classification number: H04B7/0602 , H04B1/0483 , H04B2001/0491
Abstract: In certain aspects, a method includes receiving a first intermediate frequency (IF) signal and a second IF signal via a common input, upconverting the first IF signal into a first radio frequency (RF) signal, transmitting the first RF signal via a first antenna array, upconverting the second IF signal into a second RF signal, and transmitting the second RF signal via a second antenna array. In a first transit mode, the first RF signal is in a first frequency band and the second RF signal is in a second frequency band, and, in a second transmit mode, the first RF signal and the second RF signal are both in the first frequency band.
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公开(公告)号：US20220224022A1
公开(公告)日：2022-07-14
申请号：US17653449
申请日：2022-03-03
Applicant: Qualcomm Incorporated
Inventor： Li Liu , Kevin Hsi Huai Wang , Yunfei Feng , Chuan Wang , Gurkanwal Sahota
Abstract: An apparatus is disclosed for a hybrid wireless transceiver architecture that supports multiple antenna arrays. In an example aspect, the apparatus includes a first antenna array, a second antenna array, and a wireless transceiver. The wireless transceiver includes first dedicated circuitry dedicated to the first antenna array and second dedicated circuitry dedicated to the second antenna array. The wireless transceiver also includes shared circuitry that is shared with both the first antenna array and the second antenna array.
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Patent Agency Ranking
公开(公告)号：US11025195B2
公开(公告)日：2021-06-01
申请号：US16375765
申请日：2019-04-04
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Rui Xu , Marco Vigilante , Li Liu , Xiaotie Wu
Abstract: In certain aspects, an apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on an input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing.
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公开(公告)号：US20210099197A1
公开(公告)日：2021-04-01
申请号：US17039775
申请日：2020-09-30
Applicant: Qualcomm Incorporated
Inventor： Chuan Wang , Li Liu , Kevin Hsi-Huai Wang , Bhushan Shanti Asuri , Kang Yang , Shrenik Patel
IPC: H04B1/401
Abstract: An apparatus is disclosed for transceiving signals in multiple modes. In example implementations, an apparatus includes a transceiver that includes a first amplifier; a mixer having at least one input node and at least one output node, with the at least one input node coupled to the first amplifier; and a second amplifier coupled to the at least one output node of the mixer. The transceiver also includes a first register coupled to the first amplifier and a second register coupled to the second amplifier. The transceiver further includes at least one memory realizing a lookup table. The at least one memory is coupled to the first register and the second register. The lookup table includes a first portion corresponding to a first mode of the transceiver and a second portion corresponding to a second mode of the transceiver.
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公开(公告)号：US20140273901A1
公开(公告)日：2014-09-18
申请号：US13800846
申请日：2013-03-13
Applicant: QUALCOMM INCORPORATED
Inventor： Li Liu , Steven C. Ciccarelli , Shrenik Patel , Prasad Srinivasa Siva Gudem , Zixiang Yang , Frederic Bossu , Wu-Hsin Chen , Chiewcharn Narathong
IPC: H04W52/02
CPC classification number: H04W52/0238 , Y02D70/00 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/146 , Y02D70/21 , Y02D70/24
Abstract: A method for reducing power consumption on a wireless communication device is described. The wireless communication device includes a first stage active filter and a second stage active filter. A condition measurement is obtained that includes a signal measurement condition. If it is determined that the condition measurement is above a threshold, the second stage active filter is bypassed.
Abstract translation: 描述了一种用于降低无线通信设备的功耗的方法。 无线通信装置包括第一级有源滤波器和第二级有源滤波器。 获得包括信号测量条件的条件测量。 如果确定条件测量高于阈值，则旁路第二级有源滤波器。
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9.发明授权Current-mode buffer with output swing detector for high frequency clock interconnect 有权具有输出摆幅检测器的电流模式缓冲器，用于高频时钟互连公开(公告)号：US08766674B1
公开(公告)日：2014-07-01
申请号：US13834861
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Dongmin Park , Li Liu , Sujiang Rong
Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.
Abstract translation: 高速电流模式时钟驱动器包括反馈电路，以将偏置节点的电压摆幅保持在限定的范围内。 电流模式时钟驱动器包括在其栅极端子处接收振荡信号的PMOS和NMOS晶体管。 PMOS和NMOS晶体管的漏极端子分别耦合到输出端耦合到公共节点的第一和第二可变电导率电路的输入端。 控制电路响应于公共节点的电压摆幅的减小而增加第一和第二可变电导率电路的电导率，并且响应于公共节点的电压摆幅的增加而降低第一和第二可变电导率电路的电导率。 第一和第二可变电导率电路分别是PMOS和NMOS晶体管。
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公开(公告)号：US12255586B2
公开(公告)日：2025-03-18
申请号：US18060295
申请日：2022-11-30
Applicant: Qualcomm Incorporated
Inventor： Mohamed Abouzied , Chuan Wang , Anosh Davierwalla , Muhammad Hassan , Vinod Panikkath , Li Liu
Abstract: An apparatus is disclosed for oscillator feedthrough calibration, such as a component arrangement that can be calibrated to account for signal leakage from an oscillator coupled to a mixer circuit. In example aspects, the apparatus includes a mixer circuit having a first stage, a second stage, and tuning circuitry. The first stage includes at least one transistor coupled between a mixer input and a mixer output. The second stage includes one or more transistors coupled between the at least one transistor of the first stage and the mixer output. The one or more transistors are also coupled between a local oscillator signal input and the mixer output. The tuning circuitry includes at least one current source coupled to the at least one transistor of the first stage.
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