中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.013 seconds)

    Systems and methods for wafer-level loopback test
    1.
    发明授权
    Systems and methods for wafer-level loopback test 有权

    公开(公告)号：US10114074B2

    公开(公告)日：2018-10-30

    申请号：US15955013

    申请日：2018-04-17

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  Luverne Ray Peterson

    IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

    Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

    Systems and methods to provide charge sharing at a transmit buffer circuit
    4.
    发明授权
    Systems and methods to provide charge sharing at a transmit buffer circuit 有权

    公开(公告)号：US09698782B1

    公开(公告)日：2017-07-04

    申请号：US15098129

    申请日：2016-04-13

    Applicant: QUALCOMM Incorporated

    Inventor： Luverne Ray Peterson ,  Thomas Bryan ,  Stephen Thilenius

    IPC: H03K3/00 ,  H03K19/003 ,  H03K17/16 ,  H03K19/00

    CPC classification number: H03K19/00361 ,  H03K17/162 ,  H03K19/0013 ,  H03K19/018507

    Abstract: A circuit includes a data input in communication with a first transistor stack; a first capacitor having a first capacitance and in communication with a power supply via a first transistor of the first transistor stack, wherein the first transistor is configured to charge the first capacitor in response to the data input receiving a signal corresponding to a first binary value; a data output node coupled between the first transistor stack and a transmission line having a second capacitance; and wherein the first capacitor is coupled between the data output node and a second transistor of the first transistor stack, further wherein the second transistor is configured to discharge the first capacitor to the data output node in response to the data input receiving a signal corresponding to a second binary value.

Patent Agency Ranking