公开(公告)号：US10114074B2

公开(公告)日：2018-10-30

申请号：US15955013

申请日：2018-04-17

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  Luverne Ray Peterson

IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

公开(公告)号：US09762231B2

公开(公告)日：2017-09-12

申请号：US14812516

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Bo Yu ,  Stephen Clifford Thilenius ,  Reza Jalilizeinali ,  Patrick Isakanian

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/082 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K17/0822 ,  H03K19/00315 ,  H03K19/018521

Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

公开(公告)号：US09654090B2

公开(公告)日：2017-05-16

申请号：US15138142

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K3/00 ,  H03K5/15 ,  H01L23/538 ,  G06F1/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

公开(公告)号：US11056253B2

公开(公告)日：2021-07-06

申请号：US16800949

申请日：2020-02-25

Applicant: QUALCOMM Incorporated

Inventor： Harikrishna Chintarlapalli Reddy ,  Alvin Leng Sun Loke

IPC: H01C1/01 ,  H01L27/01

Abstract: An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

公开(公告)号：US09930769B2

公开(公告)日：2018-03-27

申请号：US14181187

申请日：2014-02-14

Applicant: QUALCOMM Incorporated

Inventor： Arpit Mittal ,  Alvin Leng Sun Loke ,  Mehdi Saeidi ,  Patrick Drennan

IPC: H01L29/00 ,  H05K1/02 ,  H01C1/08 ,  H01C1/01 ,  H01L49/02 ,  H01C1/084 ,  H01L23/522 ,  H01L23/367

CPC classification number: H05K1/0204 ,  H01C1/01 ,  H01C1/08 ,  H01C1/084 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.

公开(公告)号：US20160294383A1

公开(公告)日：2016-10-06

申请号：US14792441

申请日：2015-07-06

Applicant: QUALCOMM, Incorporated

Inventor： Mohammed Mizanur Rahman ,  Jacob Stephen Schneider ,  Thomas Clark Bryan ,  LuVerne Ray Peterson ,  Gregory Francis Lynch ,  Alvin Leng Sun Loke

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03F3/45197 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45504 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03878

Abstract: A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Abstract translation: 提供了可编程均衡器和相关方法。 均衡器包括分别与第一电压轨（Vdd）和第二电压轨（地）之间的一对输入FET和一对负载电阻串联耦合的一对电流设定场效应晶体管（FET）。 可编程均衡电路耦合在输入FET的源极之间，包括多个可选择的电阻路径和可变电容器，其也可以被配置为多个可选择的电容路径。 每个可选择的电阻路径（以及每个可选择的电容路径）包括用于选择性地耦合在输入FET的源极之间的对应的电阻（或电容）路径的选择FET。 在其中一个输入FET被参考栅极电压偏置的情况下，每个选择FET的源极耦合到这种输入FET的源极。

公开(公告)号：US20160269017A1

公开(公告)日：2016-09-15

申请号：US14812516

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Bo Yu ,  Stephen Clifford Thilenius ,  Reza Jalilizeinali ,  Patrick Isakanian

IPC: H03K17/082

CPC classification number: H03K17/0822 ,  H03K19/00315 ,  H03K19/018521

Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

Abstract translation: 提供电子电路和操作电子电路的方法。 电子电路包括用于将输出电路的输入/输出（I / O）节点提升到第一电压的上拉晶体管和用于将上拉晶体管耦合到I / O节点的第一隔离晶体管。 电子电路还包括用于将I / O节点下拉到第二电压的下拉晶体管和用于将下拉晶体管耦合到I / O节点的第二隔离晶体管。 在电子电路中，上拉和下拉晶体管是支持第一漏极 - 源极电压和第一栅极 - 源极电压的晶体管，而第一和第二隔离晶体管是支撑第一漏极 并且第二栅极至源极电压大于第一栅极至源极电压。

公开(公告)号：US09350339B2

公开(公告)日：2016-05-24

申请号：US14335681

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K3/00 ,  H03K5/15 ,  H01L23/538 ,  G06F1/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。

公开(公告)号：US09245870B1

公开(公告)日：2016-01-26

申请号：US14516763

申请日：2014-10-17

Applicant: QUALCOMM Incorporated

Inventor： LuVerne Ray Peterson ,  Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Tin Tin Wee ,  Gregory Francis Lynch ,  Stephen Robert Knol

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/065 ,  G06F1/10 ,  G06F17/5072 ,  G06F2217/62 ,  G06F2217/78 ,  H01L2924/0002 ,  H04L7/0095 ,  H01L2924/00

Abstract: A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.

Abstract translation: 电路包括具有暴露的数据节点的第一阵列的第一管芯和具有暴露的数据节点的第二阵列的第二管芯，其中第一阵列的给定数据节点对应于第二阵列上的相应的数据节点，此外， 所述第一阵列和所述第二阵列共享所述数据节点的空间布置，其中所述第一裸片具有用于所述第一阵列的第一侧上的所述第一阵列的每个数据节点的数据输入和顺序逻辑电路，并且其中所述第二阵列 管芯具有用于第二阵列的第二侧上的第二阵列的每个数据节点的数据输出和顺序逻辑电路，第一和第二侧是不同的。

公开(公告)号：US10429441B2

公开(公告)日：2019-10-01

申请号：US15603779

申请日：2017-05-24

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti Chakraborty ,  Alvin Leng Sun Loke ,  Hong Dai ,  Thomas Clark Bryan

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.