公开(公告)号：US20170162235A1

公开(公告)日：2017-06-08

申请号：US14957045

申请日：2015-12-02

Applicant: QUALCOMM INCORPORATED

Inventor： SUBRATO DE ,  RICHARD STEWART ,  DEXTER TAMIO CHUN

IPC: G11C7/10 ,  G06F12/06 ,  G06F3/06 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0607 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1657 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power/performance optimization. One such method comprises configuring an interleaved zone for relatively higher performance tasks, a linear address zone for relatively lower power tasks, and a mixed interleaved-linear zone for tasks with intermediate performance requirements. A boundary is defined among the different zones using a sliding threshold address. The zones may be dynamically adjusted, and/or new zones dynamically created, by changing the sliding address in real-time based on system goals and application performance preferences. A request for high performance memory is allocated to a zone with lower power that minimally supports the required performance, or may be allocated to a low power memory zone with lower than required performance if the system parameters indicate a need for aggressive power conservation. Pages may be migrated between zones in order to free a memory device for powering down.