公开(公告)号：US20180356451A1

公开(公告)日：2018-12-13

申请号：US15710593

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jingcheng ZHUANG

IPC: G01R23/02 ,  G01R25/00

Abstract: A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedback path. This isolation improves linearity. In one instance, the PFD includes a supply voltage, one or more switches, a reference capacitor and a feedback capacitor. The reference capacitor is selectively coupled to the supply voltage via the one or more switches and the feedback capacitor is selectively coupled to the supply voltage via the one or more switches.

公开(公告)号：US20180076805A1

公开(公告)日：2018-03-15

申请号：US15265217

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh PAUL ,  Jingcheng ZHUANG ,  Xinhua CHEN ,  Ravi SRIDHARA

IPC: H03K5/156 ,  H03K21/02

CPC classification number: H03K5/1565 ,  H03K21/02

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

公开(公告)号：US20180019756A1

公开(公告)日：2018-01-18

申请号：US15272307

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Jingcheng ZHUANG ,  Xinhua CHEN ,  Frederic BOSSU ,  Yiwu TANG

IPC: H03L7/087 ,  H03L7/099 ,  H03L7/197 ,  H04L7/033

CPC classification number: H03L7/087 ,  H03L7/0898 ,  H03L7/099 ,  H03L7/191 ,  H03L7/1974 ,  H03L7/1976 ,  H04L7/033

Abstract: A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.

公开(公告)号：US20170338940A1

公开(公告)日：2017-11-23

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Mohammad ELBADRY ,  Tsai-Pi HUNG ,  Ravi SRIDHARA ,  Francesco GATTA ,  Jingcheng ZHUANG

IPC: H04L7/033 ,  H04L5/14 ,  H04L29/06 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.