公开(公告)号：US11734787B2

公开(公告)日：2023-08-22

申请号：US17478694

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Ashokanand Neelambaran ,  Piyush Gupta ,  Kalyan Kumar Bhiravabhatla ,  Tao Wang ,  Andrew Evan Gruber

IPC: G06T1/20 ,  A63F13/525 ,  G06T3/40 ,  G06T11/40

CPC classification number: G06T1/20 ,  A63F13/525 ,  G06T3/40 ,  G06T11/40

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of primitives associated with one or more frames in a scene, a portion of the scene being associated with an upscaled sample space and/or a downscaled sample space. The apparatus may also perform a binning pass for the plurality of primitives, the binning pass being associated with an unscaled sample space, where the binning pass sorts each of the primitives into one or more bins associated with each of the one or more frames. Further, the apparatus may perform one of one or more rendering passes for each of the one or more bins. The apparatus may also rasterize each of the plurality of primitives based on at least one of the upscaled sample space or the downscaled sample space.

公开(公告)号：US20250104325A1

公开(公告)日：2025-03-27

申请号：US18476258

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Vishwanath Shashikant Nikam ,  Kalyan Kumar Bhiravabhatla ,  Sampathkumar Periasamy ,  Suvam Chatterjee

IPC: G06T15/00 ,  G06T15/04

Abstract: Efficiently handling restart indices during tile-based deferred rendering (TBDR) by graphics processing units (GPUs) is disclosed herein. In some aspects, a processor circuit of a GPU determines, during a tile sorting pass, a location of a restart index in a plurality of indices of an index buffer associated with a primitive topology, and determines a skip count indicating a number of indices to skip during a tile rendering pass, based on the primitive topology and the location of the restart index. In some aspects, the processor circuit also determines visibility statuses corresponding to primitives of the primitive topology, and generates visibility data comprising the visibility statuses and the skip count. Subsequently, during the tile rendering pass, the processor circuit bypasses fetching of the restart index, based on the skip count. According to some aspects, the processor circuit may also assemble the primitives based on the visibility data.

公开(公告)号：US11682109B2

公开(公告)日：2023-06-20

申请号：US17073218

申请日：2020-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Bhiravabhatla ,  Krishnaiah Gummidipudi ,  Ankit Kumar Singh ,  Andrew Evan Gruber ,  Pavan Kumar Akkaraju ,  Srihari Babu Alla ,  Jonnala Gadda Nagendra Kumar ,  Vishwanath Shashikant Nikam

IPC: G06T5/40 ,  G06T7/13 ,  G06T1/20 ,  G06T5/20 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T5/40 ,  G06T1/20 ,  G06T5/20 ,  G06T7/13 ,  G06T15/005 ,  G06T15/40

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.

公开(公告)号：US11600002B2

公开(公告)日：2023-03-07

申请号：US16892096

申请日：2020-06-03

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Srihari Babu Alla ,  Kalyan Kumar Bhiravabhatla ,  Jonnala Gadda Nagendra Kumar ,  William Licea-Kane ,  Fredrick Alan Hickman

IPC: G06T7/11 ,  G06T1/60 ,  G06T1/20 ,  G06T7/136 ,  G06T5/40

Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

公开(公告)号：US12079897B2

公开(公告)日：2024-09-03

申请号：US17935031

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Bhiravabhatla ,  Andrew Evan Gruber ,  Rahul Sunil Kukreja ,  Vishwanath Shashikant Nikam ,  Tao Wang ,  Jian Liang

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for improving visibility generation in tile-based GPU architectures. A graphics processor may perform a first binning pass associated with visibility information for each of a plurality of primitives in at least one frame. The visibility information for each of the plurality of primitives may correspond to a visible indication or an invisible indication. The graphics processor may update a depth buffer based on the visibility information for all of the plurality of primitives in the at least one frame. The graphics processor may perform a second binning pass for each of the visible set of primitives based on the updated depth buffer. The graphics processor may store at least one of the updated visibility information or updated position data for all primitives in the visible set of primitives from the second binning pass.

公开(公告)号：US20210383545A1

公开(公告)日：2021-12-09

申请号：US16892096

申请日：2020-06-03

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Srihari Babu Alla ,  Kalyan Kumar Bhiravabhatla ,  Jonnala Gadda Nagendra Kumar ,  William Licea-Kane ,  Fredrick Alan Hickman

IPC: G06T7/11 ,  G06T7/136 ,  G06T5/40 ,  G06T1/60 ,  G06T1/20

Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

公开(公告)号：US20240078735A1

公开(公告)日：2024-03-07

申请号：US18067837

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Xuefeng Tang ,  Vishwanath Shashikant Nikam ,  Nigel Poole ,  Kalyan Kumar Bhiravabhatla ,  Fei Xu ,  Zilin Ying

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.

公开(公告)号：US11908079B2

公开(公告)日：2024-02-20

申请号：US17658634

申请日：2022-04-08

Applicant: QUALCOMM Incorporated

Inventor： Renju Boben ,  Kalyan Kumar Bhiravabhatla ,  Vishwanath Shashikant Nikam ,  Suvam Chatterjee ,  Ankit Kumar Singh ,  Abhishek Lal ,  Sampathkumar Periasamy

IPC: G06T17/20 ,  G06T15/00

CPC classification number: G06T17/20 ,  G06T15/005

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

公开(公告)号：US11893654B2

公开(公告)日：2024-02-06

申请号：US17373704

申请日：2021-07-12

Applicant: QUALCOMM Incorporated

Inventor： Sreyas Kurumanghat ,  Kalyan Kumar Bhiravabhatla ,  Andrew Evan Gruber ,  Tao Wang ,  Baoguang Yang ,  Pavan Kumar Akkaraju

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/405

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.

公开(公告)号：US11631215B2

公开(公告)日：2023-04-18

申请号：US16816150

申请日：2020-03-11

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Krishnaiah Gummidipudi ,  Pavan Kumar Akkaraju ,  Kalyan Kumar Bhiravabhatla ,  Ankit Kumar Singh ,  Sharad Raj

IPC: G06T15/50 ,  G06T1/20 ,  G06T15/00 ,  G06T7/00 ,  G06T17/10 ,  G06T17/20

Abstract: The present disclosure relates to methods and apparatus for graphics processing. The present disclosure can calculate a center-edge distance of a first pixel, the center-edge distance of the first pixel equal to a distance from a first pixel center to one or more edges of a first primitive. Additionally, the present disclosure can store the center-edge distance of the first pixel when the first primitive is visible in a scene. The present disclosure can also determine an amount of overlap between the first pixel and the first primitive. Further, the present disclosure can blend a color of the first pixel with a color of a second pixel based on at least one of the center-edge distance of the first pixel or the amount of overlap between the first pixel and the first primitive.