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公开(公告)号：US11817379B2
公开(公告)日：2023-11-14
申请号：US16927823
申请日：2020-07-13
Applicant: QUALCOMM Incorporated
Inventor： Jonghae Kim , Milind Shah , Periannan Chidambaram
CPC classification number: H01L23/49822 , H03F3/213 , H05K1/111 , H05K1/16 , H05K1/181 , H05K1/185 , H05K1/0231 , H05K1/0233
Abstract: A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.
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公开(公告)号：US11776888B2
公开(公告)日：2023-10-03
申请号：US17334610
申请日：2021-05-28
Applicant: QUALCOMM Incorporated
Inventor： Kuiwon Kang , Hong Bok We , Chin-Kwan Kim , Milind Shah
IPC: H01L23/498 , H01L21/48 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L23/49822 , H01L24/16 , H01L2224/16227 , H01L2224/16238
Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.
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公开(公告)号：US11320847B2
公开(公告)日：2022-05-03
申请号：US16804474
申请日：2020-02-28
Applicant: QUALCOMM Incorporated
Inventor： Jonghae Kim , Ravindra Vaman Shenoy , Milind Shah , Evgeni Gousev , Periannan Chidambaram
Abstract: Reducing the space occupied by a voltage regulation integrated circuit (IC) that includes an inductor is achieved by implementing the inductor as a 3D inductor having windings formed of conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with the other circuit components and with the structural layers of the voltage regulation IC. A voltage regulation IC may be a switched-mode power supply (SMPS) that includes an inductor with a capacitor and/or a switching circuit. The inductor is implemented as upper horizontal traces in an upper substrate, lower horizontal traces in a lower substrate, and vertical interconnects in a circuit layer between the upper substrate and the lower substrate, and the conductive elements form the 3D inductor as a rectangular coil.
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公开(公告)号：US11189686B2
公开(公告)日：2021-11-30
申请号：US16798161
申请日：2020-02-21
Applicant: QUALCOMM Incorporated
Inventor： Jonghae Kim , Milind Shah , Periannan Chidambaram
IPC: H01L49/02 , H01L23/498 , H01L25/065 , H01L23/31 , H01L23/48
Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and a capacitor structure located between the substrate and the integrated device. The capacitor structure includes a capacitor substrate comprising a first trench, a first electrically conductive layer located in the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer. The first electrically conductive layer over the first trench, the dielectric layer and the second electrically conductive layer are configured as a first capacitor.
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公开(公告)号：US10510733B2
公开(公告)日：2019-12-17
申请号：US16185635
申请日：2018-11-09
Applicant: QUALCOMM Incorporated
Inventor： Rajneesh Kumar , Chin-Kwan Kim , Milind Shah
IPC: H01L25/10 , H01L23/552 , H01L23/66 , H01L25/065 , H04W4/80 , H01L25/00 , H04W4/00 , H01L23/00 , H01L25/16 , H01L21/56
Abstract: A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.
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Patent Agency Ranking
公开(公告)号：US20210271275A1
公开(公告)日：2021-09-02
申请号：US16804474
申请日：2020-02-28
Applicant: QUALCOMM Incorporated
Inventor： Jonghae Kim , Ravindra Vaman Shenoy , Milind Shah , Evgeni Gousev , Periannan Chidambaram
Abstract: Reducing the space occupied by a voltage regulation integrated circuit (IC) that includes an inductor is achieved by implementing the inductor as a 3D inductor having windings formed of conductive elements integrated into a lower substrate, a circuit layer, and an upper substrate, and positioning other components within a core space of the 3D inductor in the circuit layer. The space occupied by the inductor is shared with the other circuit components and with the structural layers of the voltage regulation IC. A voltage regulation IC may be a switched-mode power supply (SMPS) that includes an inductor with a capacitor and/or a switching circuit. The inductor is implemented as upper horizontal traces in an upper substrate, lower horizontal traces in a lower substrate, and vertical interconnects in a circuit layer between the upper substrate and the lower substrate, and the conductive elements form the 3D inductor as a rectangular coil.
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公开(公告)号：US10163871B2
公开(公告)日：2018-12-25
申请号：US15097719
申请日：2016-04-13
Applicant: QUALCOMM Incorporated
Inventor： Rajneesh Kumar , Chin-Kwan Kim , Milind Shah
IPC: H01L25/10 , H01L23/552 , H01L23/66 , H01L25/065 , H04W4/80 , H01L25/00 , H04W4/00 , H01L23/00 , H01L25/16 , H01L21/56
Abstract: An integrated device that includes a printed circuit board (PCB) and a package on package (PoP) device coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package that includes a first electronic package component (e.g., first die) and a second package coupled to the first package. The integrated device includes a first encapsulation layer formed between the first package and the second package. The integrated device includes a second encapsulation layer that at least partially encapsulates the package on package (PoP) device. The integrated device is configured to provide cellular functionality, wireless fidelity functionality and Bluetooth functionality. In some implementations, the first encapsulation layer is separate from the second encapsulation layer. In some implementations, the second encapsulation layer includes the first encapsulation layer. The package on package (PoP) device includes a gap controller located between the first package and the second package.
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公开(公告)号：US11894366B2
公开(公告)日：2024-02-06
申请号：US18298211
申请日：2023-04-10
Applicant: QUALCOMM Incorporated
Inventor： Jonghae Kim , Milind Shah , Periannan Chidambaram
CPC classification number: H01L27/0805 , H01L23/642 , H01L25/0657 , H01L25/105 , H01L28/40 , H01L28/90 , H01L29/66181 , H01L29/945 , H10B12/038 , H10B12/37 , H10B12/39 , H01L2924/19041
Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.
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公开(公告)号：US11764489B2
公开(公告)日：2023-09-19
申请号：US17568596
申请日：2022-01-04
Applicant: QUALCOMM Incorporated
Inventor： Milind Shah , Chin-Kwan Kim , Jaehyun Yeon , Rajneesh Kumar , Suhyung Hwang
CPC classification number: H01Q23/00 , H01Q1/241 , H01Q1/243 , H01Q9/0414 , H01Q21/065 , H01Q21/068 , H01Q21/30
Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.
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公开(公告)号：US11652101B2
公开(公告)日：2023-05-16
申请号：US17144411
申请日：2021-01-08
Applicant: QUALCOMM Incorporated
Inventor： Jonghae Kim , Milind Shah , Periannan Chidambaram
CPC classification number: H01L27/0805 , H01L25/105 , H01L27/10829 , H01L27/10838 , H01L27/10861 , H01L28/40 , H01L28/90 , H01L29/66181 , H01L29/945
Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.
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