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    Processor Security Mode Based SoC Infrastructure Power Management
    3.
    发明申请
    Processor Security Mode Based SoC Infrastructure Power Management 有权

    公开(公告)号：US20220206559A1

    公开(公告)日：2022-06-30

    申请号：US17136175

    申请日：2020-12-29

    Applicant: QUALCOMM Incorporated

    Inventor： Bharat Kumar RANGARAJAN ,  Rajesh ARIMILLI ,  Rengarajan RAGAVAN

    IPC: G06F1/3237 ,  G06F21/74 ,  G06F3/06

    Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.

    DYNAMIC MEMORY POWER MANAGEMENT
    4.
    发明申请
    DYNAMIC MEMORY POWER MANAGEMENT 审中-公开

    公开(公告)号：US20190265778A1

    公开(公告)日：2019-08-29

    申请号：US15908534

    申请日：2018-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Raghavendra SRINIVAS ,  Bharat Kumar RANGARAJAN ,  Rajesh ARIMILLI

    IPC: G06F1/32

    Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

    DYNAMIC MEMORY POWER MANAGEMENT
    6.
    发明申请
    DYNAMIC MEMORY POWER MANAGEMENT 审中-公开

    公开(公告)号：US20200278739A1

    公开(公告)日：2020-09-03

    申请号：US15929732

    申请日：2020-05-19

    Applicant: QUALCOMM Incorporated

    Inventor： Raghavendra SRINIVAS ,  Bharat Kumar RANGARAJAN ,  Rajesh ARIMILLI

    IPC: G06F1/3296 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G11C5/14 ,  G06F1/3206 ,  G06F1/26

    Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

    CLOCK SPINE WITH TAP POINTS
    8.
    发明申请
    CLOCK SPINE WITH TAP POINTS 审中-公开

    公开(公告)号：US20170310312A1

    公开(公告)日：2017-10-26

    申请号：US15134994

    申请日：2016-04-21

    Applicant: QUALCOMM Incorporated

    Inventor： Rajesh ARIMILLI ,  Apurv NARKHEDE ,  Ajay NAWANDHAR

    IPC: H03K5/15

    CPC classification number: H03K5/15026 ,  G06F1/10 ,  G06F2207/388

    Abstract: Apparatuses and methods to relay a clock signal to clock loads are presented. An apparatus includes a clock spine to conduct a clocking signal. The clock spine includes multiple taps points distributed unevenly on the clock spine. The apparatus further includes multiple clock buffers. Each of the multiple clock buffers is connected to a corresponding one of the multiple tap points. The method includes conducting a clocking signal on a clock spine having multiple taps points. The multiple tap points are distributed unevenly on the clock spine. The method further includes buffering the clocking signal at each of the multiple tap points. Another method includes forming a clock spine to conduct a clocking signal. The clock spine includes multiple taps points. The multiple tap points are distributed unevenly on the clock spine. The method further includes forming multiple clock buffers.

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