公开(公告)号：US20170075408A1

公开(公告)日：2017-03-16

申请号：US15010237

申请日：2016-01-29

Applicant: QUALCOMM Incorporated

Inventor： Sarbartha BANERJEE ,  Rakesh MISRA

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: An apparatus includes a first circuit configured to receive one or more requests from a plurality of cores. Each of the one or more requests is to enter or to exit one of a plurality of power-down modes. The first circuit further selects one or more of the cores to enter or to exit the requested power-down mode or modes based on inrush current information associated with the power-down modes. A second circuit is configured to effect entering or exiting the requested power-down mode or modes in the selected one or more of the cores.

Abstract translation: 一种装置包括被配置为从多个核接收一个或多个请求的第一电路。 一个或多个请求中的每一个是进入或退出多个掉电模式中的一个。 第一电路还基于与掉电模式相关联的浪涌电流信息进一步选择一个或多个核进入或退出所请求的掉电模式或模式。 第二电路被配置为实现进入或退出所选择的一个或多个核心中的所请求的掉电模式或模式。

公开(公告)号：US20190138079A1

公开(公告)日：2019-05-09

申请号：US15808538

申请日：2017-11-09

Applicant: QUALCOMM Incorporated

Inventor： Rajesh ARIMILLI ,  Bharat Kumar RANGARAJAN ,  Rakesh MISRA

IPC: G06F1/32 ,  G11C11/419 ,  G11C5/14 ,  G06F13/42

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/4273 ,  G09G2330/02 ,  G11C5/14 ,  G11C5/147 ,  G11C11/419

Abstract: Systems, methods, and apparatus for operating a central processing unit (CPU) are provided. The CPU includes a plurality of memories including a first group of memories and a second group of memories. The plurality of memories are grouped based on a timing criticality of each memory. The CPU further includes a memory core (MX) voltage supply configured to provide the plurality of memories with an MX voltage, an application processor core (APC) voltage supply configured to provide the plurality of memories with an APC voltage, and a voltage switching circuit. The voltage switching circuit detects an operating mode of the CPU and switches a voltage provided to at least one of the first group of memories or the second group of memories between the MX voltage and the APC voltage based on a type of the operating mode detected.

公开(公告)号：US20200133862A1

公开(公告)日：2020-04-30

申请号：US16173221

申请日：2018-10-29

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Chulmin JUNG ,  Rakesh MISRA

IPC: G06F12/0846 ,  G06F12/0808 ,  G06F12/0891 ,  G06F12/0895

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for accessing tag information in a memory line. The techniques include determining an operation to perform on at least one memory line of a memory. The techniques further include performing the operation by accessing only a portion of the at least one memory line, wherein the only the portion of the at least one memory line comprises one or more flag bits that are independently accessible from remaining bits of the at least one memory line.

公开(公告)号：US20190212768A1

公开(公告)日：2019-07-11

申请号：US15868211

申请日：2018-01-11

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar RANGARAJAN ,  Rakesh MISRA ,  Rajesh ARIMILLI

IPC: G06F1/10 ,  G06F1/26

Abstract: Method and Apparatus for automatically switching to a low power retention mode based on architectural clock gating is disclosed. In some implementations, a system includes a central processing unit (CPU), comprising a clock gating cell configured to receive a clock enable signal. The system further includes a switching module configured to monitor the clock enable signal and to cause a power manager to switch the CPU from a first power supply output to a second power supply output in response to the clock enable signal changing from a first state to a second state.