中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.014 seconds)

    Monolithic integrated circuit (MMIC) structure and method for forming such structure
    2.
    发明授权
    Monolithic integrated circuit (MMIC) structure and method for forming such structure 有权
    单片集成电路（MMIC）结构及其形成方法

    公开(公告)号：US09082722B2

    公开(公告)日：2015-07-14

    申请号：US13849858

    申请日：2013-03-25

    Applicant: Raytheon Company

    Inventor： Adrian D. Williams ,  Paul M. Alcorn

    IPC: H01L21/311 ,  H01L29/66 ,  H01L29/812 ,  H01L21/8252 ,  H01L29/778 ,  H01L27/06 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20

    CPC classification number: H01L21/31144 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7786 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

    Abstract translation: 一种用于形成具有晶体管器件的半导体结构的方法，所述晶体管器件具有用于控制第一电极和第二电极之间的载流子流动的控制电极。 钝化层沉积在第一电极，第二电极和控制电极上。 蚀刻停止层沉积在控制电极上的钝化层上。 在蚀刻停止层上方形成介电层。 通过控制电极上的电介质层中的选定区域蚀刻窗口，以暴露设置在控制电极上的蚀刻停止层的一部分。 在蚀刻停止层的一部分上形成金属层，并且还在金属层上形成电介质层。 第二金属层沉积在形成在第一金属层上的电介质层的部分上。

    MONOLITHIC INTEGRATED CIRCUIT (MMIC) STRUCTURE AND METHOD FOR FORMING SUCH STRUCTURE
    5.
    发明申请
    MONOLITHIC INTEGRATED CIRCUIT (MMIC) STRUCTURE AND METHOD FOR FORMING SUCH STRUCTURE 有权
    单片集成电路（MMIC）结构和形成这种结构的方法

    公开(公告)号：US20140284661A1

    公开(公告)日：2014-09-25

    申请号：US13849858

    申请日：2013-03-25

    Applicant: RAYTHEON COMPANY

    Inventor： Adrian D. Williams ,  Paul M. Alcorn

    IPC: H01L21/311 ,  H01L29/812 ,  H01L29/66

    CPC classification number: H01L21/31144 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7786 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.

    Abstract translation: 一种用于形成具有晶体管器件的半导体结构的方法，所述晶体管器件具有用于控制第一电极和第二电极之间的载流子流动的控制电极。 钝化层沉积在第一电极，第二电极和控制电极上。 蚀刻停止层沉积在控制电极上的钝化层上。 在蚀刻停止层上方形成介电层。 通过控制电极上的电介质层中的选定区域蚀刻窗口，以暴露设置在控制电极上的蚀刻停止层的一部分。 在蚀刻停止层的一部分上形成金属层，并且还在金属层上形成介电层。 第二金属层沉积在形成在第一金属层上的电介质层的部分上。

    REDUCED JUNCTION AREA BARRIER-BASED PHOTODETECTOR
    8.
    发明申请
    REDUCED JUNCTION AREA BARRIER-BASED PHOTODETECTOR 有权
    减少接线面积基于光栅的照相机

    公开(公告)号：US20150263204A1

    公开(公告)日：2015-09-17

    申请号：US14630046

    申请日：2015-02-24

    Applicant: RAYTHEON COMPANY

    Inventor： Edward P. Smith ,  Borys P. Kolasa ,  Paul M. Alcorn

    IPC: H01L31/0352 ,  H01L31/103 ,  H01L31/18

    CPC classification number: H01L31/0352 ,  H01L31/09 ,  H01L31/101

    Abstract: A photodetector structure having a barrier layer disposed between a pair of like-conductively doped semiconductor layers, the barriers layer having a surface area smaller than the surface area of the upper one of the pair of semiconductor layers. A fill material is disposed between outer peripheral edges of the barrier layer and a region between outer peripheral edges of the first and second layers.

    Abstract translation: 一种光电检测器结构，其具有设置在一对类似导电掺杂的半导体层之间的阻挡层，所述势垒层的表面积小于所述一对半导体层的上部表面积的表面积。 填充材料设置在阻挡层的外围边缘与第一和第二层的外围边缘之间的区域之间。

Patent Agency Ranking