公开(公告)号：US20170309728A1

公开(公告)日：2017-10-26

申请号：US15468862

申请日：2017-03-24

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya YOSHIDA ,  Tetsuo ITO ,  Koji OGATA ,  Hideki AONO

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/266 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66568 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/78603

Abstract: In a process of implanting ions of an n-type impurity for threshold control into a semiconductor substrate surrounded by an element isolation portion, a resist pattern is formed such that the resist pattern covers a divot formed at a boundary portion of the element isolation portion with an SOI layer. Thus, since ions of the n-type impurity are not implanted into the divot, an etching rate of the divot in a cleaning process or the like is not accelerated, and etching can be suppressed. As a result, a BOX layer is prevented from becoming thin, so that degradation of a TDDB characteristic of the BOX layer can be prevented.

公开(公告)号：US20180277459A1

公开(公告)日：2018-09-27

申请号：US15871793

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Naohito SUZUMURA ,  Hideki AONO

IPC: H01L23/367 ,  H01L23/528 ,  H01L27/092 ,  H01L23/50 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/367 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0211 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L2027/11874

Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

公开(公告)号：US20170092555A1

公开(公告)日：2017-03-30

申请号：US15280308

申请日：2016-09-29

Applicant: Renesas Electronics Corporation

Inventor： Hideki AONO ,  Makoto OGASAWARA ,  Naohito SUZUMURA ,  Tetsuya YOSHIDA

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G01R31/2621 ,  G01R31/2628 ,  G01R31/2642 ,  H01L22/14 ,  H01L22/26 ,  H01L29/785

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

公开(公告)号：US20150109046A1

公开(公告)日：2015-04-23

申请号：US14506621

申请日：2014-10-04

Applicant: Renesas Electronics Corporation

Inventor： Noritaka Fukuo ,  Hideki AONO ,  Eiichi Murakami

IPC: H03K17/284 ,  H03K17/30

CPC classification number: H03K17/284 ,  H03K17/145 ,  H03K17/302

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract translation: 防止P沟道MOS晶体管的NBTI故障。 半导体集成电路装置包括复位脉冲控制单元RPC。 复位脉冲控制单元RPC产生复位脉冲RP，以从在待机状态下接收晶体管的栅极处的负电压的MOS晶体管的NBTI引起的劣化恢复。 在产生的复位脉冲RP被输入到MOS晶体管的栅极之后，用于激活MOS晶体管的动作控制信号ACC被输入到MOS晶体管的栅极以激活晶体管。

公开(公告)号：US20190198402A1

公开(公告)日：2019-06-27

申请号：US16291620

申请日：2019-03-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki AONO ,  Tetsuya YOSHIDA ,  Makoto OGASAWARA ,  Shinichi OKAMOTO

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/76237 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

公开(公告)号：US20160141289A1

公开(公告)日：2016-05-19

申请号：US14934745

申请日：2015-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki AONO ,  Tetsuya YOSHIDA ,  Makoto OGASAWARA ,  Shinichi OKAMOTO

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/76237 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6659

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract translation: 提供具有提高的可靠性的半导体器件。 主要由氧化硅组成的元件隔离区被埋在形成于半导体衬底中的沟槽中。 由元件隔离区包围的有源区中的半导体衬底在其上具有用于MISFET的栅极经由栅极绝缘膜。 栅电极部分地延伸在元件隔离区上方，并且沟槽具有氮化的内表面。 在栅电极下方，氟被引入到元件隔离区域和MISFET的沟道区域之间的边界附近。