公开(公告)号：US20210313467A1

公开(公告)日：2021-10-07

申请号：US17353079

申请日：2021-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20180069119A1

公开(公告)日：2018-03-08

申请号：US15806535

申请日：2017-11-08

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11 ,  H01L27/108 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/3215

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20160315192A1

公开(公告)日：2016-10-27

申请号：US15201744

申请日：2016-07-05

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/49 ,  H01L27/108

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20250098281A1

公开(公告)日：2025-03-20

申请号：US18966471

申请日：2024-12-03

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20200227557A1

公开(公告)日：2020-07-16

申请号：US16835661

申请日：2020-03-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20170104099A1

公开(公告)日：2017-04-13

申请号：US15384000

申请日：2016-12-19

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L27/11 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/3215

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.