公开(公告)号：US20160056254A1

公开(公告)日：2016-02-25

申请号：US14931000

申请日：2015-11-03

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu OTA ,  Hirokazu SAYAMA ,  Hidekazu ODA

IPC: H01L29/423 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20240395823A1

公开(公告)日：2024-11-28

申请号：US18795310

申请日：2024-08-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20180069119A1

公开(公告)日：2018-03-08

申请号：US15806535

申请日：2017-11-08

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11 ,  H01L27/108 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/3215

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20160315192A1

公开(公告)日：2016-10-27

申请号：US15201744

申请日：2016-07-05

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/49 ,  H01L27/108

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20150061006A1

公开(公告)日：2015-03-05

申请号：US14459999

申请日：2014-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi SHINOHARA ,  Hidekazu ODA ,  Toshiaki IWAMATSU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Abstract translation: 在具有通过绝缘层形成在半导体衬底上的半导体层的SOI衬底中，在nMIS形成区域和pMIS形成区域中的每个半导体层中形成MISFET。 在供电区域中，去除半导体层和绝缘层。 在半导体基板中，形成p型半导体区域，以便包括nMIS形成区域和一个供电区域，并且形成n型半导体区域以便包括pMIS形成区域，而另一个 的供电区域。 在半导体衬底中，形成具有比p型半导体区域低的杂质浓度的p型阱，以便容纳p型半导体区域，并且具有比n型半导体的杂质浓度低的n型阱 区域形成为包含n型半导体区域。

公开(公告)号：US20250098281A1

公开(公告)日：2025-03-20

申请号：US18966471

申请日：2024-12-03

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20230282647A1

公开(公告)日：2023-09-07

申请号：US18317500

申请日：2023-05-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki TSUNOMURA ,  Yoshiki YAMAMOTO ,  Masaaki SHINOHARA ,  Toshiaki IWAMATSU ,  Hidekazu ODA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834 ,  H01L27/1207 ,  H01L21/823418

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US20200227557A1

公开(公告)日：2020-07-16

申请号：US16835661

申请日：2020-03-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11 ,  H01L29/49

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20170104099A1

公开(公告)日：2017-04-13

申请号：US15384000

申请日：2016-12-19

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu OHTA ,  Hidekazu ODA ,  Kouhei SUGIHARA

IPC: H01L29/78 ,  H01L27/11 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/3215

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20170040226A1

公开(公告)日：2017-02-09

申请号：US15299216

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Hidekazu ODA

IPC: H01L21/84 ,  H01L21/265 ,  H01L27/12 ,  H01L21/822 ,  H01L29/66

CPC classification number: H01L29/6656 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.

Abstract translation: 为了提高具有完全耗尽的SOI晶体管的半导体器件的可靠性和性能，而形成在栅电极的侧壁上的偏移间隔物的宽度被配置为大于或等于半导体层的厚度并且更小 除了半导体层的厚度和绝缘膜的厚度的总和的厚度以外，杂质被离子注入到未被栅电极和偏移间隔物覆盖的半导体层中。 因此，通过离子注入杂质形成的延伸层不会从低于栅电极的端部的位置进入沟道。