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    MEMORY ERROR REPAIR
    2.
    发明申请
    MEMORY ERROR REPAIR 有权
    内存错误修复

    公开(公告)号：US20150339202A1

    公开(公告)日：2015-11-26

    申请号：US14717048

    申请日：2015-05-20

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Vlad Fruchter ,  Chi-Ming Yeung

    IPC: G06F11/20

    CPC classification number: G11C29/765 ,  G06F3/0629 ,  G06F11/0751 ,  G06F11/1008 ,  G11C5/04 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/56008 ,  G11C29/88 ,  G11C2029/4402

    Abstract: In response to a first memory access transaction having a first base address, data fields and a repair fields are retrieved from a first DRAM channel. The data fields include a first data field. The repair fields include a first repair field storing repair data. The repair data is to replace any data in the first data field. In response to a second memory access transaction having a second base address, repair tag fields are retrieved from a second DRAM channel. The repair tag fields include a repair tag field that indicates the repair data is be replace the data stored in the first data field.

    Abstract translation: 响应于具有第一基地址的第一存储器访问事务，从第一DRAM信道检索数据字段和修复字段。 数据字段包括第一数据字段。 修复领域包括存储修复数据的第一修复区域。 修复数据将替换第一个数据字段中的任何数据。 响应于具有第二基地址的第二存储器访问事务，从第二DRAM信道检索修复标签字段。 修复标签字段包括修复标签字段，其指示修复数据被替换存储在第一数据字段中的数据。

    Power saving driver design
    4.
    发明授权
    Power saving driver design 有权
    省电驱动设计

    公开(公告)号：US08922245B2

    公开(公告)日：2014-12-30

    申请号：US13963122

    申请日：2013-08-09

    Applicant: Rambus Inc.

    Inventor： Kyung Suk Oh ,  Chi-Ming Yeung ,  David A. Secker

    IPC: H03K3/012 ,  G11C7/10 ,  H04L25/02 ,  G11C11/4074

    CPC classification number: H03K3/012 ,  G11C7/1057 ,  G11C11/4074 ,  H04L25/028

    Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.

    Abstract translation: 在不对称端接的通信系统中，基于输出位是否是具有相同值的第二，第三，第四等等的连续位，在输出特定位值之后，调整发送特定位值所消耗的功率 。 可以通过在具有相同值的第二个或后续的连续位中调整驱动器强度来进行用于传送具有相同值的两个或更多个连续位的消耗的功率的调整。 消耗功率的调整是对消耗最多DC功率的比特值进行的，另一个值通常不被调整。

    Memory system design using buffer(s) on a mother board
    8.
    发明授权
    Memory system design using buffer(s) on a mother board 有权

    公开(公告)号：US10169258B2

    公开(公告)日：2019-01-01

    申请号：US15071072

    申请日：2016-03-15

    Applicant: Rambus Inc.

    Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

    IPC: G06F13/20 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

    Memory system design using buffer(s) on a mother board
    10.
    发明授权
    Memory system design using buffer(s) on a mother board 有权

    公开(公告)号：US11537540B2

    公开(公告)日：2022-12-27

    申请号：US17316586

    申请日：2021-05-10

    Applicant: Rambus Inc.

    Inventor： Chi-Ming Yeung ,  Yoshie Nakabayashi ,  Thomas Giovannini ,  Henry Stracovsky

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

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