公开(公告)号：US20210336627A1

公开(公告)日：2021-10-28

申请号：US17315699

申请日：2021-05-10

Applicant: Rambus Inc.

Inventor： Masum HOSSAIN ,  Kenneth C. DYER ,  Nhat NGUYEN ,  Shankar TANGIRALA

IPC: H03M1/00 ,  H04L25/03

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

公开(公告)号：US20230253974A1

公开(公告)日：2023-08-10

申请号：US18092564

申请日：2023-01-03

Applicant: Rambus Inc.

Inventor： Masum HOSSAIN ,  Kenneth C. DYER ,  Nhat NGUYEN ,  Shankar TANGIRALA

IPC: H03M1/00 ,  H04L25/03

CPC classification number: H03M1/002 ,  H04L25/03038 ,  H04L25/03 ,  H03M1/007 ,  H03M1/145

Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.