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公开(公告)号：US20180248577A1
公开(公告)日：2018-08-30
申请号：US15755255
申请日：2016-10-12
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Nhat NGUYEN , Yikui Jen DONG , Arash ZARGARAN-YAZD , Wendemagegnehu BEYENE
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US20210143798A1
公开(公告)日：2021-05-13
申请号：US16952553
申请日：2020-11-19
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Carl W. WERNER
Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
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公开(公告)号：US20200382103A1
公开(公告)日：2020-12-03
申请号：US16901767
申请日：2020-06-15
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Carl W. WERNER
Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
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公开(公告)号：US20220190808A1
公开(公告)日：2022-06-16
申请号：US17559960
申请日：2021-12-22
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Carl W. WERNER
Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
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公开(公告)号：US20210336627A1
公开(公告)日：2021-10-28
申请号：US17315699
申请日：2021-05-10
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Kenneth C. DYER , Nhat NGUYEN , Shankar TANGIRALA
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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Patent Agency Ranking
公开(公告)号：US20200153468A1
公开(公告)日：2020-05-14
申请号：US16680859
申请日：2019-11-12
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Nhat NGUYEN , Yikui Jen DONG , Arash ZARGARAN-YAZD , Wendemagegnehu BEYENE
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US20230353177A1
公开(公告)日：2023-11-02
申请号：US18144342
申请日：2023-05-08
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Nhat NGUYEN , Yikui Jen DONG , Arash ZARGARAN-YAZD , Wendemagegnehu BEYENE
CPC classification number: H04B1/123 , H04L25/03057 , H04L25/4917 , H04L27/06 , H04L27/01 , H04B1/12 , H04L27/00 , H04L25/03133 , H04L25/0264 , H04L25/03076
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US20220149876A1
公开(公告)日：2022-05-12
申请号：US17527631
申请日：2021-11-16
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Nhat NGUYEN , Yikui Jen DONG , Arash ZARGARAN-YAZD , Wendemagegnehu BEYENE
IPC: H04B1/12
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US20210152205A1
公开(公告)日：2021-05-20
申请号：US17114782
申请日：2020-12-08
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Nhat NGUYEN , Yikui Jen DONG , Arash ZARGARAN-YAZD , Wendemagegnehu BEYENE
Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.
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公开(公告)号：US20190007189A1
公开(公告)日：2019-01-03
申请号：US16032616
申请日：2018-07-11
Applicant: Rambus Inc.
Inventor： Masum HOSSAIN , Brian Leibowitz , Jihong Ren
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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