公开(公告)号：US12074609B2

公开(公告)日：2024-08-27

申请号：US17687765

申请日：2022-03-07

申请人： Regents of the University of Minnesota

发明人： Zhi Yang ,  Anh Tuan Nguyen ,  Diu Khue Luu ,  Jian Xu

IPC分类号： H03M1/66 ,  H03M1/00 ,  H03M1/44 ,  H03M1/46 ,  H03M1/80

CPC分类号： H03M1/46 ,  H03M1/007 ,  H03M1/447 ,  H03M1/802

摘要： A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.

公开(公告)号：US20230261914A1

公开(公告)日：2023-08-17

申请号：US17927516

申请日：2021-05-20

申请人： ORANGE

发明人： Alexandre Ferrieux ,  Fabrice Guillemin ,  Veronica Karina Quintuna Rodriguez

IPC分类号： H04L25/49 ,  H04L1/00 ,  H03M1/00

CPC分类号： H04L25/4927 ,  H04L1/0002 ,  H04L1/0006 ,  H04L1/0045 ,  H04L1/0075 ,  H03M1/007

摘要： A method for quantizing data representative of a radio signal received by a radio antenna of a mobile network. The method includes: demodulating the radio signal received by the antenna, providing a demodulated signal; scalar quantizing each value of the demodulated signal using a quantization table selected according to a channel coding level used to transmit the radio signal, providing a quantized demodulated signal; and transmitting the quantized demodulated signal to a channel decoding module.

公开(公告)号：US20180198461A1

公开(公告)日：2018-07-12

申请号：US15915796

申请日：2018-03-08

申请人： Microchip Technology Incorporated

发明人： Bryan Kris ,  Neil Deutscher ,  Thomas S. Spohrer

IPC分类号： H03M1/34 ,  H03M1/10 ,  H03K5/131 ,  H03K5/14 ,  H03K5/00

CPC分类号： H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

摘要： Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

公开(公告)号：US10009035B1

公开(公告)日：2018-06-26

申请号：US15495572

申请日：2017-04-24

申请人： Marc-Andre LaCroix ,  Semyon Lebedev ,  Henry Wong ,  Davide Tonietto

发明人： Marc-Andre LaCroix ,  Semyon Lebedev ,  Henry Wong ,  Davide Tonietto

IPC分类号： H03M1/06 ,  H03M1/08 ,  H04B1/38 ,  H03M1/12 ,  H04L25/06 ,  H03M1/00

CPC分类号： H04B1/38 ,  H03M1/00 ,  H03M1/007 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/46 ,  H04L25/067

摘要： Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

公开(公告)号：US09906235B2

公开(公告)日：2018-02-27

申请号：US15484987

申请日：2017-04-11

申请人： Microchip Technology Incorporated

发明人： Bryan Kris

IPC分类号： H03M1/12 ,  H03M1/10 ,  H03M1/38 ,  H03K5/131 ,  H03K5/14 ,  H03K5/00

CPC分类号： H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

摘要： Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

公开(公告)号：US20170294917A1

公开(公告)日：2017-10-12

申请号：US15484987

申请日：2017-04-11

申请人： Microchip Technology Incorporated

发明人： Bryan Kris

IPC分类号： H03M1/10 ,  H03K5/131 ,  H03K5/14 ,  H03M1/38

CPC分类号： H03M1/34 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03M1/007 ,  H03M1/1009 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/18 ,  H03M1/38 ,  H03M1/502

摘要： Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

公开(公告)号：US09136868B1

公开(公告)日：2015-09-15

申请号：US14466300

申请日：2014-08-22

申请人： Nokia Corporation

发明人： Hans Danneels

IPC分类号： H03M1/12 ,  H03M3/00 ,  H03M1/36 ,  H03M1/06 ,  H03M1/00

CPC分类号： H03M3/46 ,  H03M1/00 ,  H03M1/007 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/126 ,  H03M1/365 ,  H03M1/44

摘要： An improved analog to digital converter comprises at least one delta sigma analog to digital converter stage and a succession of pipelined analog to digital converter stages. The pipelined analog to digital converter stages may have a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage. The sampling rate of the at least one delta sigma analog to digital converter stage may be an oversampling rate. The sampling rate of the at least one delta-sigma analog to digital converter stages and the pipeline stages may be adjusted by adjusting their sampling frequency and the number of effective pipeline stages may be adjusted—for example, by adjusting a sampling frequency input at each stage. The effective number of pipeline stages may be adjusted, for example, based on the precision needed to process the current signal.

摘要翻译： 改进的模数转换器包括至少一个Δ-Σ模数转换器级和一系列流水线模数转换器级。 流水线模数转换器级可以具有与至少一个delta-sigma模数转换器级的采样速率分开的采样速率。 至少一个Δ-Σ模数转换器级的采样率可以是过采样率。 可以通过调整其采样频率来调整至少一个Δ-Σ模数转换器级和流水线级的采样率，并且可以调整有效流水线级的数量 - 例如，通过调整每个 阶段。 可以例如基于处理电流信号所需的精度来调整流水线级的有效数量。

公开(公告)号：US20150103220A1

公开(公告)日：2015-04-16

申请号：US14573978

申请日：2014-12-17

申请人： OMNIVISION TECHNOLOGIES, INC.

发明人： Zheng Yang ,  Guangbin Zhang ,  Yuanbao Gu

IPC分类号： H04N5/378 ,  H04N5/357 ,  H04N5/369 ,  H03M1/10 ,  H03M1/56

CPC分类号： H04N5/378 ,  H03M1/007 ,  H03M1/10 ,  H03M1/1009 ,  H03M1/1042 ,  H03M1/123 ,  H03M1/56 ,  H03M1/58 ,  H03M2201/2355 ,  H04N5/2175 ,  H04N5/357 ,  H04N5/3698 ,  H04N5/3745

摘要： An apparatus includes analog-to-digital (A/D) conversion circuitry coupled to a pixel array. The A/D conversion circuitry includes a voltage ramp generator and a set of column A/D conversion circuits. The voltage ramp generator generates a single slope voltage ramp in a first state and a multiple slope voltage ramp in a second state. The set of column A/D conversion circuits is coupled with the voltage ramp generator. The apparatus further includes calibration circuitry coupled with the set of column A/D conversion circuits and operable to determine digital calibration data to adjust digital image data. The calibration circuitry provides analog calibration data that spans a calibration range to the set of column A/D conversion circuits instead of the analog image data from the pixel array being provided to the set of column A/D conversion circuits.

摘要翻译： 一种装置包括耦合到像素阵列的模数（A / D）转换电路。 A / D转换电路包括电压斜坡发生器和一组列A / D转换电路。 电压斜坡发生器产生处于第一状态的单斜坡电压斜坡和处于第二状态的多斜坡电压斜坡。 该列A / D转换电路与电压斜坡发生器耦合。 该装置还包括与一组列A / D转换电路耦合的校准电路，并且可操作以确定数字校准数据以调整数字图像数据。 校准电路提供将校准范围跨越到A / D转换电路组的模拟校准数据，而不是提供给列A / D转换电路的像素阵列的模拟图像数据。

公开(公告)号：US08994832B1

公开(公告)日：2015-03-31

申请号：US14573978

申请日：2014-12-17

申请人： OmniVision Technologies, Inc.

发明人： Zheng Yang ,  Guangbin Zhang ,  Yuanbao Gu

IPC分类号： H04N5/378 ,  H03M1/10 ,  H03M1/56 ,  H04N5/369 ,  H04N5/357 ,  H04N5/217 ,  H04N5/3745

CPC分类号： H04N5/378 ,  H03M1/007 ,  H03M1/10 ,  H03M1/1009 ,  H03M1/1042 ,  H03M1/123 ,  H03M1/56 ,  H03M1/58 ,  H03M2201/2355 ,  H04N5/2175 ,  H04N5/357 ,  H04N5/3698 ,  H04N5/3745

摘要： An apparatus includes analog-to-digital (A/D) conversion circuitry coupled to a pixel array. The A/D conversion circuitry includes a voltage ramp generator and a set of column A/D conversion circuits. The voltage ramp generator generates a single slope voltage ramp in a first state and a multiple slope voltage ramp in a second state. The set of column A/D conversion circuits is coupled with the voltage ramp generator. The apparatus further includes calibration circuitry coupled with the set of column A/D conversion circuits and operable to determine digital calibration data to adjust digital image data. The calibration circuitry provides analog calibration data that spans a calibration range to the set of column A/D conversion circuits instead of the analog image data from the pixel array being provided to the set of column A/D conversion circuits.

摘要翻译： 一种装置包括耦合到像素阵列的模数（A / D）转换电路。 A / D转换电路包括电压斜坡发生器和一组列A / D转换电路。 电压斜坡发生器产生处于第一状态的单斜坡电压斜坡和处于第二状态的多斜坡电压斜坡。 该列A / D转换电路与电压斜坡发生器耦合。 该装置还包括与一组列A / D转换电路耦合的校准电路，并且可操作以确定数字校准数据以调整数字图像数据。 校准电路提供将校准范围跨越到A / D转换电路组的模拟校准数据，而不是提供给列A / D转换电路的像素阵列的模拟图像数据。

公开(公告)号：US08941527B2

公开(公告)日：2015-01-27

申请号：US14257832

申请日：2014-04-21

申请人： OmniVision Technologies, Inc.

发明人： Zheng Yang ,  Guangbin Zhang ,  Yuanbao Gu

IPC分类号： H03M1/82 ,  H03M1/12 ,  H03M1/56 ,  H04N5/228 ,  H04N5/217 ,  H04N3/14 ,  H04N5/225 ,  H04N5/378 ,  H03M1/10

CPC分类号： H04N5/378 ,  H03M1/007 ,  H03M1/10 ,  H03M1/1009 ,  H03M1/1042 ,  H03M1/123 ,  H03M1/56 ,  H03M1/58 ,  H03M2201/2355 ,  H04N5/2175 ,  H04N5/357 ,  H04N5/3698 ,  H04N5/3745

摘要： A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

摘要翻译： 一个方面的方法包括以像素阵列获取模拟图像数据，并从像素阵列中读出模拟图像数据。 通过使用多个斜坡电压斜坡进行模数（A / D）转换，将模拟图像数据转换成数字图像数据。 用校准数据调整至少一些数字图像数据。 还公开了其它方法，装置和系统。