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    System and method for providing a low power low voltage data detection circuit for RF AM signals in EPC0 compliant RFID tags
    1.
    发明授权
    System and method for providing a low power low voltage data detection circuit for RF AM signals in EPC0 compliant RFID tags 有权
    在EPC0兼容RFID标签中为RF AM信号提供低功耗低电压数据检测电路的系统和方法

    公开(公告)号：US07579906B2

    公开(公告)日：2009-08-25

    申请号：US11044748

    申请日：2005-01-27

    申请人： Ravi Kumar ,  Priyanka Agarwal ,  V. Pravin Kumar

    发明人： Ravi Kumar ,  Priyanka Agarwal ,  V. Pravin Kumar

    IPC分类号： H03D1/04

    CPC分类号： H03D1/18

    摘要： A system and method is disclosed for demodulating RF amplitude modulated signals in a demodulator circuit of an EPC0 compliant RFID tag. One advantageous embodiment of the invention comprises first and second input ports, a +ve envelope detector circuit for each of the first and second input ports, a −ve envelope detector circuit for each of the first and second input ports, a +ve envelope differentiator circuit, a +ve low pass filter, a −ve envelope differentiator circuit, a −ve low pass filter, and a zero crossing detector. The zero crossing detector detects a transition in the RF input signal using a voltage difference between a +ve filtered differentiated envelope signal and a −ve filtered differentiated envelope signal.

    摘要翻译： 公开了一种用于在EPC0兼容RFID标签的解调器电路中解调RF幅度调制信号的系统和方法。 本发明的一个有利实施例包括第一和第二输入端口，用于第一和第二输入端口中的每一个的+ ve包络检测器电路，用于第一和第二输入端口中的每一个的-ve包络检测器电路，+ ve包络微分器 电路，+ ve低通滤波器，a -ve包络微分电路，a -ve低通滤波器和零交叉检测器。 过零检测器使用+ ve滤波的微分包络信号和经过滤波的差分包络信号之间的电压差来检测RF输入信号中的转变。

    System and method for providing a low power low voltage data detection circuit for RF AM signals in EPC0 compliant RFID tags
    2.
    发明申请
    System and method for providing a low power low voltage data detection circuit for RF AM signals in EPC0 compliant RFID tags 有权
    在EPC0兼容RFID标签中为RF AM信号提供低功耗低电压数据检测电路的系统和方法

    公开(公告)号：US20060103457A1

    公开(公告)日：2006-05-18

    申请号：US11044748

    申请日：2005-01-27

    申请人： Ravi Kumar ,  Priyanka Agarwal ,  V. Kumar

    发明人： Ravi Kumar ,  Priyanka Agarwal ,  V. Kumar

    IPC分类号： H03D1/00

    CPC分类号： H03D1/18

    摘要： A system and method is disclosed for demodulating RF amplitude modulated signals in a demodulator circuit of an EPCO compliant RFID tag. One advantageous embodiment of the invention comprises first and second input ports, a +ve envelope detector circuit for each of the first and second input ports, a −ve envelope detector circuit for each of the first and second input ports, a +ve envelope differentiator circuit, a +ve low pass filter, a −ve envelope differentiator circuit, a −ve low pass filter, and a zero crossing detector. The zero crossing detector detects a transition in the RF input signal using a voltage difference between a +ve filtered differentiated envelope signal and a −ve filtered differentiated envelope signal.

    摘要翻译： 公开了用于在EPCO兼容RFID标签的解调器电路中解调RF幅度调制信号的系统和方法。 本发明的一个有利实施例包括第一和第二输入端口，用于第一和第二输入端口中的每一个的+ ve包络检测器电路，用于第一和第二输入端口中的每一个的-ve包络检测器电路，+ ve包络微分器 电路，+ ve低通滤波器，a -ve包络微分电路，a -ve低通滤波器和零交叉检测器。 过零检测器使用+ ve滤波的微分包络信号和经过滤波的差分包络信号之间的电压差来检测RF输入信号中的转变。

    N-bit constant adder/subtractor
    3.
    发明申请
    N-bit constant adder/subtractor 有权
    N位常数加法器/减法器

    公开(公告)号：US20060161614A1

    公开(公告)日：2006-07-20

    申请号：US11262496

    申请日：2005-10-27

    申请人： Tarun Vashishta ,  Priyanka Agarwal

    发明人： Tarun Vashishta ,  Priyanka Agarwal

    IPC分类号： G06F7/50

    CPC分类号： G06F7/5055 ,  G06F7/5057

    摘要： An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.

    摘要翻译： 在FPGA上实现的N位常数系数加法器/减法器的区域有效实现，利用具有单输出生成能力的N个LUT。 它包括来自每个LUT的三个输入用于加法/减法，而不需要额外的逻辑来支持算术模式和进位链。 对于支持4输入LUT的FPGA，通过利用LUT的第四个未使用的输入，动态地执行加法和减法的能力进一步增强了概念。 另一个实施例涉及在具有4输入LUT的FPGA上实现的N位常数系数加法器/减法器的延迟优化实现。 实现中的LUT具有单输出生成能力，无需任何进位生成和传播。 该实现使用N + 1个LUT并给出与所使用的路由资源的N / 2成比例的延迟。 然而，通过使用级联链，实现变得更加有效。 延迟优化通过在两个并行链中进行计算来实现。

    N-bit constant adder/subtractor
    5.
    发明授权
    N-bit constant adder/subtractor 有权
    N位常数加法器/减法器

    公开(公告)号：US07689643B2

    公开(公告)日：2010-03-30

    申请号：US11262496

    申请日：2005-10-27

    申请人： Tarun Kumar Vashishta ,  Priyanka Agarwal

    发明人： Tarun Kumar Vashishta ,  Priyanka Agarwal

    IPC分类号： G06F7/50

    CPC分类号： G06F7/5055 ,  G06F7/5057

    摘要： An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic for support of arithmetic mode and carry chains. For FPGAs supporting 4-input LUTs, the concept is further enhanced with the capability to perform addition and subtraction dynamically, by exploiting the fourth unused input of the LUTs. Another embodiment involves delay-optimized realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs with 4-input LUTs. LUTs in the implementation have single output generation capability without any carry generation and propagation. The implementation utilizes N+1 LUTs and gives a delay proportional to N/2 of routing resource used. However, the implementation becomes more efficient by the use of cascade chains. The delay optimization is achieved by doing computation in two parallel chains.

    摘要翻译： 在FPGA上实现的N位常数系数加法器/减法器的区域有效实现，利用具有单输出生成能力的N个LUT。 它包括来自每个LUT的三个输入用于加法/减法，而不需要额外的逻辑来支持算术模式和进位链。 对于支持4输入LUT的FPGA，通过利用LUT的第四个未使用的输入，动态地执行加法和减法的能力进一步增强了概念。 另一个实施例涉及在具有4输入LUT的FPGA上实现的N位常数系数加法器/减法器的延迟优化实现。 实现中的LUT具有单输出生成能力，无需任何进位生成和传播。 该实现使用N + 1个LUT并给出与所使用的路由资源的N / 2成比例的延迟。 然而，通过使用级联链，实现变得更加有效。 延迟优化通过在两个并行链中进行计算来实现。