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    Filtering a read signal to attenuate secondary pulses caused by pole tips of a thin film magnetic read head
    1.
    发明授权
    Filtering a read signal to attenuate secondary pulses caused by pole tips of a thin film magnetic read head 失效
    滤除读取信号以衰减由薄膜磁头读取头的极尖引起的次脉冲

    公开(公告)号：US5623377A

    公开(公告)日：1997-04-22

    申请号：US222666

    申请日：1994-04-04

    申请人： Richard T. Behrens ,  Neal Glover ,  Trent O. Dudley ,  Alan J. Armstrong ,  Christopher P. Zook ,  William G. Bliss

    发明人： Richard T. Behrens ,  Neal Glover ,  Trent O. Dudley ,  Alan J. Armstrong ,  Christopher P. Zook ,  William G. Bliss

    IPC分类号： G11B5/09 ,  G11B20/10 ,  H03H17/02 ,  H03H17/06 ,  H04B3/06 ,  G11B5/035

    CPC分类号： H03H17/06 ,  G11B20/10009 ,  G11B5/09 ,  H03H17/02

    摘要： A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput. Further, the pre-cursor correcting portion of the filter can be disabled in order to avoid delaying the data stream while still canceling the post-cursor secondary pulses. The filter also comprises attenuation and adder means to match the coincident sample values in amplitude and add them to substantially eliminate the effect of the secondary pulses in the discrete data stream.

    摘要翻译： 用于补偿与从磁介质读取的数据产生的离散主脉冲的数据流相关联的离散次级脉冲形成的滤波器。 滤波器的脉冲响应包括具有侧补偿系数的中心系数，用于当输入信号与脉冲响应卷积时衰减次级脉冲。 补偿系数的幅度和延迟可编程，并进行自适应调整，以优化给定环境的脉冲响应。 在传统的FIR实施例中，使用两条延迟线来产生中心系数和侧面补偿系数之间的两个可编程延迟。 在优选实施例中，IIR滤波器仅使用一个延迟线提供两个可编程延迟，从而减小电路的尺寸和成本。 同样在优选实施例中，数据流被交织成偶数和奇数数据流，并且由两个滤波器并行处理，以使吞吐量翻倍。 此外，可以禁用滤波器的前光标校正部分，以避免在仍然取消后光标次级脉冲的同时延迟数据流。 滤波器还包括衰减和加法器装置，以使幅度上重合的采样值相匹配，并将它们相加，以基本上消除离散数据流中次级脉冲的影响。

    Low data delay triple coverage code apparatus for on-the-fly error correction
    4.
    发明授权
    Low data delay triple coverage code apparatus for on-the-fly error correction 失效
    低数据延迟三重覆盖码设备，用于即时纠错

    公开(公告)号：US5268908A

    公开(公告)日：1993-12-07

    申请号：US717677

    申请日：1991-06-19

    申请人： Neal Glover ,  David R. Hieb ,  Trent O. Dudley ,  Dennis L. Baker

    发明人： Neal Glover ,  David R. Hieb ,  Trent O. Dudley ,  Dennis L. Baker

    IPC分类号： G06F11/10 ,  H03M13/29

    CPC分类号： G06F11/10 ,  H03M13/29

    摘要： The low-data-delay triple-coverage code for on-the-fly error correction apparatus allows on-the-fly error correction with fewer redundancy bytes than needed for a non-overlaid data redundancy structure thereby producing corrected data with a low data delay. The present apparatus divides a received block of data into a plurality of fixed size sub-blocks with the last sub-block size being smaller than or equal to the fixed sub-block size. Three predefined error correcting code generator polynomials are used to accumulate redundancy values for the sub-blocks. At the end of each sub-block one of the three pre-defined error correcting code generator polynomials will have accumulated a redundancy value across the present sub-block data and the previous two sub-blocks of data and redundancy. After the accumulated redundancy has been output as write data the predefined error correcting code generator polynomial is reset. Therefore, the redundancy information contained in each sub-block covers that sub-block's data in addition to the data and redundancy in the previous two sub-blocks.

    摘要翻译： 用于即时纠错装置的低数据延迟三重覆盖代码允许以非覆盖数据冗余结构所需的冗余字节更少的冗余字节进行即时纠错，从而产生具有低数据延迟的校正数据 。 本装置将接收到的数据块划分为多个固定大小子块，其中最后一个子块大小小于或等于固定子块大小。 三个预定义的纠错码生成多项式用于累加子块的冗余值。 在每个子块的末尾，三个预定义的纠错码生成多项式中的一个将在当前子块数据和前两个数据和冗余子块之间累积冗余值。 在积累的冗余被输出为写入数据之后，复位预定义的纠错码生成多项式。 因此，除了前两个子块中的数据和冗余之外，每个子块中包含的冗余信息覆盖该子块的数据。

    Synchronous read channel
    5.
    发明授权
    Synchronous read channel 失效
    同步读通道

    公开(公告)号：US07957370B2

    公开(公告)日：2011-06-07

    申请号：US12126188

    申请日：2008-05-23

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    IPC分类号： H04L12/50

    CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

    摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

    摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

    Synchronous read channel employing a data randomizer
    6.
    发明授权
    Synchronous read channel employing a data randomizer 失效
    采用数据随机化器的同步读通道

    公开(公告)号：US5844509A

    公开(公告)日：1998-12-01

    申请号：US820926

    申请日：1997-03-19

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31 ,  H03M7/46

    CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

    摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation. When the Data Randomizer is enabled, the probability of encountering any specific pattern of length n channel bits at a randomly selected location within encoded data is approximately 1/2.sup.n.

    摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 读通道采用数据随机化器，其处理未编码的用户数据，以确保具有最坏情况模式灵敏度的信道位模式不会比从随机用户数据预期的更频繁地发生。 数据随机化器采用两个线性反馈移位寄存器：一个产生一个63位的序列，它与每对数据位的MSB相对而言是EXLUSIVE-OR-，另一个产生一个127位的序列，它是独占 每对数据位的LSB。 Data Randomizer不影响错误传播。 当启用数据随机器时，在编码数据内随机选择的位置遇到长度为n个通道位的任何特定模式的概率大约为+ E，fra 1/2 + EE n。

    Gain control circuit for synchronous waveform sampling
    7.
    发明授权
    Gain control circuit for synchronous waveform sampling 失效
    用于同步波形采样的增益控制电路

    公开(公告)号：US5297184A

    公开(公告)日：1994-03-22

    申请号：US12049

    申请日：1993-02-01

    申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

    IPC分类号： G11B5/09 ,  G11B20/10 ,  H03G3/20 ,  H04L27/08

    CPC分类号： H03G3/001 ,  G11B20/10009 ,  H03G3/3036

    摘要： A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.

    摘要翻译： 一种混合的模拟和数字增益控制电路，用于控制模拟输入信号的幅度。 该电路具有可变增益放大器，其接收来自读/写记录头前置放大器的信号。 可变增益放大器的输出通过多路复用器和均衡器连接到模数转换器，用于在受控采样时将模拟信号转换为数字采样值。 增益控制电路接收指示何时发生脉冲的数字值和脉冲检测器的输出。 增益控制电路内的增益误差检测器确定每个检测脉冲幅度的误差量，并将该误差量滤波并通过数模转换器发送，然后通过取幂电路。 指数电路的输出连接到可变增益放大器的增益控制输入。

    SYNCHRONOUS READ CHANNEL
    8.
    发明申请
    SYNCHRONOUS READ CHANNEL 失效
    同步读通道

    公开(公告)号：US20080285549A1

    公开(公告)日：2008-11-20

    申请号：US12126188

    申请日：2008-05-23

    申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

    IPC分类号： H04L12/50

    CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

    摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

    摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。