公开(公告)号：US20250022758A1

公开(公告)日：2025-01-16

申请号：US18424111

申请日：2024-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongho KIM ,  Sunoo KIM ,  Jinwoo KIM ,  Boin NOH ,  Sejun PARK ,  Jaehee OH

IPC: H01L21/66 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate, a connection pad disposed on an interlayer insulating layer and electrically connected to an interconnection structure, a passivation layer disposed on the connection pad and having a first opening and a second opening, each exposing at least a portion of the connection pad, a first bump that includes a first lower conductive layer in contact with the connection pad within the first opening and a first upper conductive layer on the first lower conductive layer, and a second bump that includes a second lower conductive layer in contact with the connection pad within the second opening and a second upper conductive layer on the second lower conductive layer. The first and second lower conductive layers include the same material, and the first upper conductive layer and the second upper conductive layer include different materials.

公开(公告)号：US20230230944A1

公开(公告)日：2023-07-20

申请号：US17959352

申请日：2022-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boin NOH ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/73 ,  H01L24/08 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2924/3511 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/73253 ,  H01L2224/08148 ,  H01L2224/05655 ,  H01L2224/05541 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05573 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166

Abstract: A semiconductor package includes a second semiconductor chip disposed on a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate, a through via, and a lower pad disposed on the through via. The lower pad includes a first segment and a second segment connected thereto. The first segment overlaps the through via. The second segment is disposed on an edge region of the first segment. The second segment has an annular shape. The second semiconductor chip includes a second semiconductor substrate, an upper pad disposed on a bottom surface of the second semiconductor substrate, and a connection terminal disposed between the upper and lower pads. The second segment at least partially surrounds a lateral surface of the upper pad. A level of a top surface of the second segment is higher than that of an uppermost portion of the connection terminal.

公开(公告)号：US20240304504A1

公开(公告)日：2024-09-12

申请号：US18598077

申请日：2024-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boin NOH ,  Yongho KIM ,  Sunoo KIM

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/08146 ,  H01L2224/08155 ,  H01L2224/16146 ,  H01L2224/16157 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A semiconductor package includes: a semiconductor chip including an active layer; a bump pad positioned on the active layer; a passivation layer covering the bump pad and including a first opening and a second opening, wherein the first opening exposes a first portion of the second surface of the bump pad, and the second opening exposes a second portion of the second surface of the bump pad; a first bump disposed on the first portion of the second surface of the bump pad, which is exposed through the first opening; and a test bump disposed on the second portion of the second surface of the bump pad, which is exposed through the second opening, wherein the first bump includes at least one metal layer, and a length of the test bump in a vertical direction is less than a length of the first bump in the vertical direction.

公开(公告)号：US20210151380A1

公开(公告)日：2021-05-20

申请号：US16853910

申请日：2020-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boin NOH

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package including a semiconductor chip having a chip pad thereon; a first insulating layer; a redistribution line pattern on the first insulating layer; a redistribution via pattern through the first insulating layer to connect the chip pad to the redistribution line pattern; a second insulating layer covering the redistribution line pattern and including a first part having a first thickness and a second part having a second thickness. the second part being inward relative to the first part; a first conductive pillar through the first part and connected to the redistribution line pattern; a second conductive pillar through the second part and connected to the redistribution line pattern; a first connection pad on the first conductive pillar; a second connection pad on the second conductive pillar; a first connection terminal contacting the first connection pad; and a second connection terminal contacting the second connection pad.