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公开(公告)号：US10204686B2
公开(公告)日：2019-02-12
申请号：US15871322
申请日：2018-01-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Yun Lee , Chae-Hoon Kim
Abstract: A page buffer includes a first precharge circuit, a second precharge circuit, and a sense amplifying circuit. The first precharge circuit includes a first path for precharging a bitline connected to a nonvolatile memory cell. The second precharge circuit includes a second path for precharging a sensing node connected to the bitline. The second path is electrically separated from the first path. The sensing node is used to detect a state of the nonvolatile memory cell. The sense amplifying circuit is connected to the sensing node and the second precharge circuit, and stores state information representing the state of the nonvolatile memory cell. The second precharge circuit is configured to perform a first precharge operation for the sensing node and configured to selectively perform a second precharge operation for the sensing node based on the state of the nonvolatile memory cell after the first precharge operation.
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2.发明授权Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation 有权具有用于执行读写（RWW）操作和读取 - 修改 - 写入（RMW）操作的读取电路的非易失性存储器件公开(公告)号：US09135994B2
公开(公告)日：2015-09-15
申请号：US14171873
申请日：2014-02-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Hoi-Ju Chung , Chae-Hoon Kim , Yong-Jin Kwon , Eun-Hye Park , Yong-Jun Lee
CPC classification number: G11C13/004 , G11C13/0002 , G11C13/0004 , G11C13/0061 , G11C2213/72
Abstract: A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.
Abstract translation: 非易失性存储器件包括具有多个非易失性存储单元的存储器阵列，第一读取电路和第二读取电路。 第一读取电路被配置为在第一读取操作期间从存储器阵列读取第一数据，并且在第一读取操作期间提供指示受害时段的一个或多个保护信号。 第二读取电路被配置为在第二读取操作期间从存储器阵列读取第二数据，并且在第二读取操作期间提供指示侵略者周期的一个或多个检查信号。
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