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    Memory devices, memory systems and methods of operating memory devices
    1.
    发明授权
    Memory devices, memory systems and methods of operating memory devices 有权

    公开(公告)号：US10937519B2

    公开(公告)日：2021-03-02

    申请号：US16813889

    申请日：2020-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Jun Lee ,  Tae-Hui Na ,  Chea-Ouk Lim

    IPC: G11C29/44 ,  G06F11/10 ,  G11C8/10 ,  G11C29/00 ,  G11C29/52

    Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

    MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING MEMORY DEVICES
    2.
    发明申请
    MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING MEMORY DEVICES 审中-公开

    公开(公告)号：US20190156909A1

    公开(公告)日：2019-05-23

    申请号：US16128879

    申请日：2018-09-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong-Jun Lee ,  Tae-Hui Na ,  Chea-Ouk Lim

    IPC: G11C29/44 ,  G11C29/00 ,  G11C8/10 ,  G06F11/10

    Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.

    Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation
    3.
    发明授权
    Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation 有权
    具有用于执行读写（RWW）操作和读取 - 修改 - 写入（RMW）操作的读取电路的非易失性存储器件

    公开(公告)号：US09135994B2

    公开(公告)日：2015-09-15

    申请号：US14171873

    申请日：2014-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo-Jin Kwon ,  Hoi-Ju Chung ,  Chae-Hoon Kim ,  Yong-Jin Kwon ,  Eun-Hye Park ,  Yong-Jun Lee

    IPC: G11C7/22 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2213/72

    Abstract: A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

    Abstract translation: 非易失性存储器件包括具有多个非易失性存储单元的存储器阵列，第一读取电路和第二读取电路。 第一读取电路被配置为在第一读取操作期间从存储器阵列读取第一数据，并且在第一读取操作期间提供指示受害时段的一个或多个保护信号。 第二读取电路被配置为在第二读取操作期间从存储器阵列读取第二数据，并且在第二读取操作期间提供指示侵略者周期的一个或多个检查信号。

    Nonvolatile memory device and related method for reducing access latency
    6.
    发明授权
    Nonvolatile memory device and related method for reducing access latency 有权
    非易失性存储器件和相关方法，用于减少访问延迟

    公开(公告)号：US09093146B2

    公开(公告)日：2015-07-28

    申请号：US14171849

    申请日：2014-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Eun-Hye Park ,  Hoi-Ju Chung ,  Yong-Jin Kwon ,  Hyo-Jin Kwon ,  Yong-Jun Lee

    IPC: G11C8/18 ,  G11C13/00

    CPC classification number: G11C13/0061 ,  G11C13/0002 ,  G11C13/004 ,  G11C2213/72

    Abstract: A nonvolatile memory device comprises a memory core comprising a plurality of variable resistance memory cells, an input/output (I/O) circuit configured to receive a first packet signal and a second packet signal in sequence, the first and second packet signals collectively comprising information for a memory access operation, and further configured to initiate a core access operation upon decoding the first packet signal and to selectively continue or discontinue the core access operation upon decoding the second packet signal, and a read circuit configured to perform part of the core access operation in response to the first packet signal before the second packet signal is decoded.

    Abstract translation: 非易失性存储器件包括存储器芯，其包括多个可变电阻存储器单元，输入/输出（I / O）电路被配置为依次接收第一分组信号和第二分组信号，第一和第二分组信号共同地包括 用于存储器访问操作的信息，并且还被配置为在解码所述第一分组信号时发起核心访问操作，并且在解码所述第二分组信号时选择性地继续或中断所述核心访问操作;以及读取电路，被配置为执行所述核心的一部分 在第二分组信号被解码之前响应于第一分组信号的接入操作。

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