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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11521977B2

    公开(公告)日：2022-12-06

    申请号：US17471824

    申请日：2021-09-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

    Semiconductor devices with alignment keys
    3.
    发明授权
    Semiconductor devices with alignment keys 有权

    公开(公告)号：US10026694B2

    公开(公告)日：2018-07-17

    申请号：US15608747

    申请日：2017-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

    IPC: H01L23/544 ,  H01L27/108

    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

    Semiconductor devices with alignment keys
    5.
    发明授权
    Semiconductor devices with alignment keys 有权

    公开(公告)号：US10332842B2

    公开(公告)日：2019-06-25

    申请号：US16026937

    申请日：2018-07-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok Lee ,  Sooho Shin ,  Juik Lee ,  Jun Ho Lee ,  Kwangmin Kim ,  Ilyoung Moon ,  Jemin Park ,  Bumseok Seo ,  Chan-Sic Yoon ,  Hoin Lee

    IPC: H01L23/544 ,  H01L27/108

    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

    Semiconductor devices having supporter structures
    6.
    发明授权
    Semiconductor devices having supporter structures 有权

    公开(公告)号：US12015064B2

    公开(公告)日：2024-06-18

    申请号：US17683765

    申请日：2022-03-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoin Lee ,  Kiseok Lee

    IPC: H01L29/423 ,  H01L29/40

    CPC classification number: H01L29/423 ,  H01L29/402

    Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

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