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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210057419A1

    公开(公告)日：2021-02-25

    申请号：US16833919

    申请日：2020-03-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

    IPC分类号： H01L27/108

    摘要： A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230389289A1

    公开(公告)日：2023-11-30

    申请号：US18171171

    申请日：2023-02-17

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： SEOKHAN PARK ,  KISEOK LEE ,  SEOKHO SHIN ,  HYUNGEUN CHOI ,  BOWON YOO

    IPC分类号： H10B12/00

    CPC分类号： H10B12/315 ,  H10B12/482 ,  H10B12/488 ,  H10B12/05

    摘要： A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.

    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220375941A1

    公开(公告)日：2022-11-24

    申请号：US17574666

    申请日：2022-01-13

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： KISEOK LEE ,  HUI-JUNG KIM ,  MIN HEE CHO

    IPC分类号： H01L27/108 ,  H01L29/786

    摘要： A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220246180A1

    公开(公告)日：2022-08-04

    申请号：US17481583

    申请日：2021-09-22

    申请人： Samsung Electronics Co., Ltd.

    发明人： WONSOK LEE ,  MIN TAE RYU ,  WOO BIN SONG ,  KISEOK LEE ,  MINSU LEE ,  MIN HEE CHO

    IPC分类号： G11C5/06 ,  H01L29/06 ,  H01L27/108

    摘要： A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210296237A1

    公开(公告)日：2021-09-23

    申请号：US17097337

    申请日：2020-11-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： HYO-SUB KIM ,  SOHYUN PARK ,  DAEWON KIM ,  DONGOH KIM ,  EUN A KIM ,  CHULKWON PARK ,  TAEJIN PARK ,  KISEOK LEE ,  SUNGHEE HAN

    IPC分类号： H01L23/535 ,  H01L27/108 ,  H01L23/532 ,  H01L21/768

    摘要： A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.