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公开(公告)号：US11811364B2
公开(公告)日：2023-11-07
申请号：US17845378
申请日：2022-06-21
发明人： Jaehong Jung , Seunghyun Oh , Jinhyeon Lee , Gihyeok Ha , Seungjin Kim , Joomyoung Kim , Yelim Youn , Jaehoon Lee
CPC分类号： H03B5/32 , G06F1/06 , H03B5/04 , H03B5/20 , H03B2200/0082
摘要： A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.
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2.发明授权公开(公告)号：US11777510B2
公开(公告)日：2023-10-03
申请号：US17964377
申请日：2022-10-12
发明人： Baekmin Lim , Seungjin Kim , Seunghyun Oh
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/093
摘要： A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.
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公开(公告)号：US11435780B2
公开(公告)日：2022-09-06
申请号：US16743656
申请日：2020-01-15
发明人： Sungjun Lee , Seungjin Kim , Jiyong Kim , Jungchul An , Joungmin Cho , Kwangtai Kim , Donghyun Yeom
IPC分类号： G06F1/16 , G09G3/20 , H04N13/106
摘要： In an electronic device and a method for operating the electronic device according to various embodiments, an electronic device may include a foldable housing including a hinge, a first housing connected to the hinge, and a second housing connected to the hinge and configured to be foldable with the first housing about the hinge, a display including a bent area in a state in which the first housing and the second housing are folded with respect to each other, a processor disposed in the first housing or the second housing and operatively connected to the display, and a memory operatively connected to the processor, and the memory may be configured to store instructions that, when executed, cause the processor to control the electronic device to: identify a folding degree between the first housing and the second housing, generate a first image based on mapping data in which the folding degree and characteristics of the first image are mapped, generate a synthetic image of the first image and a second image corresponding to the bent area wherein the generated first image is overlaid in at least a partial area of the second image, and display the generated synthetic image.
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公开(公告)号：US11004428B2
公开(公告)日：2021-05-11
申请号：US16558904
申请日：2019-09-03
发明人： Seungjin Kim , Joonyung Park , Kwangrae Cho
摘要： Disclosed is an electronic device that includes a display, a memory, and a processor configured to combine a plurality of images based on an execution of a plurality of applications so that the plurality of images is displayed in a single screen form, identify coordinate information of a display area of each of a first image and a second image on the screen based on the first image and second image belonging to the plurality of images and being updated, store the first image and the second image in a contiguous address of the memory, and transmit the coordinate information of the display area of each of the first image and the second image and the stored first image and second image to the display.
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公开(公告)号：US10804907B2
公开(公告)日：2020-10-13
申请号：US16290067
申请日：2019-03-01
发明人： Seungjin Kim , Jihyun Kim , Taeik Kim
摘要： A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.
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公开(公告)号：US12118262B2
公开(公告)日：2024-10-15
申请号：US17703347
申请日：2022-03-24
发明人： Seungjin Kim , Sungjun Lee , Jungbae Kim , Joonyung Park , Jiesoon Jeong , Mooyoung Kim
CPC分类号： G06F3/1423 , G06T3/40 , G06T3/60
摘要： An electronic device is provided. The electronic device includes a first display disposed on a first surface of the electronic device, a second display disposed on a second surface of the electronic device and having at least a portion thereof being unviewable to a user according to a folding state of the electronic device, a memory configured to store instructions, and a processor electrically connected to the first display, the second display, and the memory. The processor is configured to execute the instructions to detect a change in the folding state of the electronic device while displaying a first image on one of the first display or the second display, when the change in the folding state is detected, generate a second image to be displayed on the other of the first display or the second display, while generating the second image, store a snapshot image of the first image in the memory and display the snapshot image on the other of the first display or the second display, and when the second image is generated, display the second image on the other of the first display or the second display instead of the snapshot image.
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公开(公告)号：US11818879B2
公开(公告)日：2023-11-14
申请号：US17901210
申请日：2022-09-01
发明人： Cheonbae Kim , Seungjin Kim , Dongkyun Lee
IPC分类号： H01L27/108 , H01L49/02 , H01L29/78 , H10B12/00
CPC分类号： H10B12/30 , H01L28/60 , H01L29/7802
摘要： A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.
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公开(公告)号：US20230217646A1
公开(公告)日：2023-07-06
申请号：US17820231
申请日：2022-08-16
发明人： Jung-Bum Lim , Seungjin Kim , Sangchul Yang , Jeon Il Lee , Hoin Lee
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10814 , H01L28/91 , H01L28/92 , H01L27/10855 , H01L28/75
摘要： A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.
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公开(公告)号：US11462610B2
公开(公告)日：2022-10-04
申请号：US16947090
申请日：2020-07-17
发明人： Yoonyoung Choi , Byunghyun Lee , Byeongjoo Ku , Seungjin Kim , Sangjae Park , Jinwoo Bae , Hangeol Lee , Bowo Choi , Hyunsil Hong
IPC分类号： H01L27/108 , H01L49/02
摘要： Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.
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公开(公告)号：US11380286B2
公开(公告)日：2022-07-05
申请号：US17155132
申请日：2021-01-22
发明人： Gwanghui Lee , Minwoo Kim , Seungjin Kim , Minwoo Lee , Juseok Lee , Woojun Jung
摘要： According to an embodiment, an electronic device may include at least one processor, a display, a memory configured to store image frames, and a display controller configured to output the image frames. The at least one processor may be configured to transmit a first image frame to be output through the display, based on a first timing signal received from the display controller, identify a state of the electronic device, transmit first control information for changing a timing of the first timing signal, in response to transmitting the first control information for changing the timing of the first timing signal, receive a second timing signal from the display controller, and transmit, to the memory, a second image frame to be output through the display, based on the received second timing signal. The timing of the second timing signal may differ from the timing of the first timing signal.
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