公开(公告)号：US20210193654A1

公开(公告)日：2021-06-24

申请号：US16927636

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beomjin PARK ,  Dongil BAE ,  Daewon KIM ,  Taeyoung KIM ,  Joohee JUNG ,  Jaehoon SHIN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.

公开(公告)号：US20210313442A1

公开(公告)日：2021-10-07

申请号：US17060193

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongseok SUH ,  Daewon KIM ,  Beomjin PARK ,  Sukhyung PARK ,  Sungil PARK ,  Jaehoon SHIN ,  Bongseob YANG ,  Junggun YOU ,  Jaeyun LEE

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.

公开(公告)号：US20220367513A1

公开(公告)日：2022-11-17

申请号：US17878304

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin SONG ,  Beyounghyun KOH ,  Yongjin KWON ,  Kangmin KIM ,  Jaehoon SHIN ,  JoongShik SHIN ,  Sungsoo AHN ,  Seunghwan LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

公开(公告)号：US20220123001A1

公开(公告)日：2022-04-21

申请号：US17348172

申请日：2021-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin KIM ,  Jaehoon SHIN ,  Dongseog EUN ,  Geunwon LIM

IPC: H01L27/11526 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a first substrate; devices on the first substrate; a second substrate on the devices; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, extending in the first direction, and including a channel layer; isolation regions penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the devices; a barrier structure spaced apart from the through contact plug and surrounding the through contact plug; and a support structure on the gate electrodes and including support patterns, wherein the support structure has first through regions spaced apart from each other in the second direction on the isolation regions and a second through region in contact with an upper surface of the barrier structure.

公开(公告)号：US20210320125A1

公开(公告)日：2021-10-14

申请号：US17162408

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon SHIN ,  Kangmin KIM ,  Kyeongjin PARK ,  Seungmin SONG ,  Joongshik SHIN ,  Geunwon LIM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522

Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

公开(公告)号：US20210111188A1

公开(公告)日：2021-04-15

申请号：US16895364

申请日：2020-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin SONG ,  Beyounghyun KOH ,  Yongjin KWON ,  Kangmin KIM ,  Jaehoon SHIN ,  JoongShik SHIN ,  Sungsoo AHN ,  Seunghwan LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.